electronic_eel_ has quit [Ping timeout: 258 seconds]
electronic_eel has joined #glasgow
tomtastic has quit [Ping timeout: 260 seconds]
tomtastic_ has joined #glasgow
Stormwind_mobile has quit [Ping timeout: 256 seconds]
Foxyloxy has quit [Quit: Leaving]
Foxyloxy has joined #glasgow
m4ssi has joined #glasgow
m4ssi has quit [Remote host closed the connection]
ec0_ is now known as ec0
Foxyloxy has quit [Quit: Leaving]
samlittlewood has quit [Quit: samlittlewood]
Foxyloxy has joined #glasgow
Stormwind_mobile has joined #glasgow
Foxyloxy has quit [Quit: Leaving]
Foxyloxy has joined #glasgow
ali_as has joined #glasgow
ali_as has quit [Ping timeout: 240 seconds]
m4ssi has joined #glasgow
tomtastic_ is now known as tomtastic
Stormwind_mobile has quit [Remote host closed the connection]
Stormwind_mobile has joined #glasgow
bvernoux has joined #glasgow
m4ssi has quit [Remote host closed the connection]
m4ssi has joined #glasgow
m4ssi has quit [Remote host closed the connection]
bvernoux has quit [Quit: Leaving]
bvernoux has joined #glasgow
<d1b2>
<MattHuszagh> Hello. I'm interested in using a glasgow as a sort of general-purpose logic analyzer. I'm trying to debug an FPGA design in hardware (simulation works as expected). I was hoping to hook up the IO pins of the glasgow to the IO pins exposed to the FPGA, trigger on some digital transition and then record all IOs for some duration of time. Is this possible? Is there some existing code I can use as a starting point?
<d1b2>
<MattHuszagh> I was hoping to get out a VCD file that I can view in gtkwave
<ktemkin>
MattHuszagh: you can use the glasgow "analyzer" applet
<ktemkin>
"glasgow run analyzer -h" for help
<d1b2>
<MattHuszagh> @Kate Temkin thanks for the pointer! I’ll look into that
uovo has joined #glasgow
oeuf has quit [Ping timeout: 265 seconds]
arisum has quit [Ping timeout: 246 seconds]
emilazy has quit [Ping timeout: 240 seconds]
arisum has joined #glasgow
emilazy has joined #glasgow
analprolapse has quit [Ping timeout: 244 seconds]
lukego has quit [Ping timeout: 244 seconds]
arisum has quit [Ping timeout: 244 seconds]
yuriks has quit [Ping timeout: 246 seconds]
carlomaragno has quit [Ping timeout: 246 seconds]
futarisIRCcloud has quit [Ping timeout: 260 seconds]
levi has quit [Ping timeout: 256 seconds]
key2 has quit [Ping timeout: 256 seconds]
eddyb[legacy] has quit [Ping timeout: 244 seconds]
nmolo has quit [Ping timeout: 246 seconds]
englishm has quit [Ping timeout: 272 seconds]
_florent_ has quit [Ping timeout: 260 seconds]
deanforbes has quit [Ping timeout: 260 seconds]
sorear has quit [Ping timeout: 244 seconds]
kc8apf has quit [Ping timeout: 272 seconds]
ktemkin has quit [Ping timeout: 246 seconds]
esden has quit [Ping timeout: 260 seconds]
evck_ has quit [Ping timeout: 272 seconds]
emilazy has quit [Ping timeout: 244 seconds]
jacob| has quit [Ping timeout: 260 seconds]
flammit has quit [Ping timeout: 272 seconds]
<d1b2>
<MattHuszagh> Does "--keep-voltage" place signal I/O pins into a high-Z state?
<whitequark>
no
<d1b2>
<MattHuszagh> ah, glad i asked
<whitequark>
well, not exactly. --voltage, --mirror-voltage and --keep-voltage only affect the IO standard of the port, and the voltage you can draw from the port if you connect to the power output
<whitequark>
whether the I/O pins are high-Z or not is determined by the applet
<d1b2>
<MattHuszagh> I see, so presumably the analyzer applet will put the I/O pins into high-Z?
<whitequark>
indeed
<whitequark>
(or rather, it does not enable the outputs; high-Z is the default)
<_whitenotifier-b>
[glasgow] FFY00 commented on issue #69: Can we get SWIM/SWD support? - https://git.io/JJt5w
<d1b2>
<MattHuszagh> great. As for the I/O standard, I only connected the grounds of my board to the glasgow ground. Otherwise I connected the signal lines. The FPGA I/O standard I'm using is 3.3V LVCMOS. Does that mean I'm supposed to use --voltage 3.3
<d1b2>
<MattHuszagh> ?
<_whitenotifier-b>
[glasgow] whitequark commented on issue #69: Can we get SWIM/SWD support? - https://git.io/JJt5y
<whitequark>
yes
<d1b2>
<MattHuszagh> thanks!
<_whitenotifier-b>
[glasgow] FFY00 commented on issue #69: Can we get SWIM/SWD support? - https://git.io/JJt5b