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<whitequark> MattHuszagh: which board revision do you have?
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<d1b2> <MattHuszagh> revC1 (revision from about 9 months ago). I found that port A actually works, but I get the pull resistor error for port B. I also still get a USB EP6IN and EP8IN timeout for the loopback selftest. I haven't forgotten your suggestion about FLAGA..FLAGD and A0..1, but I wasn't able to see any soldering issues on the cypress chip, and I'm reluctant to desolder the FPGA until I've excluded the other possibilities, since I don't yet have a good way of
<d1b2> reballing a BGA.
<d1b2> <MattHuszagh> I also saw the issue you created about the timeouts, but I checked the yosys revision I have and that should be fine
<d1b2> <MattHuszagh> In any event, unless this sounds familiar to you, it sounds like there is just still some short or open somewhere on the board I haven't found. I will keep looking
<whitequark> yes, your issues with pulls and EP*IN seem like board issues
<whitequark> actually, if it's both EP6IN and EP8IN it might be some other pins too
<whitequark> nSLWR
<whitequark> which issue about the timeouts?
<d1b2> <MattHuszagh> just in regard to EP8IN
<d1b2> <MattHuszagh> ok thanks for the heads, I'll check that too
<d1b2> <MattHuszagh> heads up about that pin**
<whitequark> oh yeah that issue has been long fixed
<d1b2> <MattHuszagh> Cool. Separately, is there a way to trigger the analyzer applet on a signal edge, so it doesn't just record from when it's run?
<whitequark> not (yet)
<whitequark> *no(t yet)
<whitequark> it's not really clear to me how the UI should look like; but we can fairly easily add e.g. continuous and timed captures, and some triggers
<d1b2> <MattHuszagh> gotcha. To clarify that I'm currently using the interface correctly, --pins-i takes a bit slice notation, like 0 or 0:7, which sets the I/O pins to record?
<whitequark> yep
<d1b2> <MattHuszagh> Cool. While you’re considering the interface, it seems to me that one nice feature would be to be able to map the pins to different names, allowing the ability to construct multibit signals from arbitrary pins. I know gtkwave has an alias feature to change the name, but I’m not sure about grouping individual signals into multibit signals. Just a thought.
<whitequark> that's pretty tough UI-wise
<whitequark> i'm not very fond of the contortions required to get this out of argparse, but... i also don't have a better replacement
<whitequark> a long term goal is to replace argparse in glasgow with something nicer, probably bespoke
<whitequark> but i'm really busy with nmigen and will remain so in the next several months
<d1b2> <MattHuszagh> fair enough
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