<bshah|matrix>
At one point I had done a lima dump as well
<bshah|matrix>
Although best do it latest now
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<bshah|matrix>
Btw I'll provide you with logs and testing if blending function fails this weekend, today I'm traveling out for KDE Akademy
<anarsoul>
OK
<anarsoul>
have a safe trip :)
<MoeIcenowy>
retested on Lima on Android
<MoeIcenowy>
seems that still largely broken
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<mardestan>
My memory is vague how to map the shader object into some buffer object in gl2.1 or es2, the intention is:
<mardestan>
access the machine instructions from vram, write a shader with mali offline compiler to checksum the stuff, integrate the pass to the compiler (done on gpu this time to chekcsum the instructions)
<mardestan>
later write the shader in mali offline assembler to run the checksums. integrate that one to the toolkit as well.
<mardestan>
anarsoul: branches and flow control is not needed with this method though, overall gpu branching is pretty numb and pointless stuff.
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<mardestan>
such thing could be done on binary drivers too, the method, i try to hack this together for IOS, LINUX and other platforms.
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<mardestan>
i can not remember how to trigger in the binary blobs in es2 level, well the checksum shader should be fairly easy
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<anarsoul>
enunes: so we can spill only vec4 registers?
<enunes>
on my experiments we can spill any size, as long as we don't have to swizzle
<enunes>
so we can spill with vec1 or even vec2 alignment, but it must be .x or .xy
<anarsoul>
that's crazy.
<anarsoul>
I can't believe they added this limitation
<enunes>
I can't convince the offline compiler to show me some other way
<enunes>
loading is ok as we load to ^uniform and can swizzle then in the reading instruction
<enunes>
for store, it seems to be the least bad way as any other way would require creating a separate instruction, while this way it can be easily merged
<anarsoul>
can we just store whole reg as is and unswizzle it when loading?
<anarsoul>
should work fine for SSAs
<anarsoul>
but not for regs though
<enunes>
I think it's pretty much what is happening now, there is no is_head limitation for the read
<anarsoul>
it doesn't really matter if it's read or write, it's a single reg (or ssa) and you set is_head then it can only be at the beginning of register
<enunes>
yes, it seems like the best solution so far
<anarsoul>
are there any regressions in piglit?
<enunes>
I have tested this with piglit, piglit forced spilling 1,2,3 times
<enunes>
also with modified cost calculation to make it exercise vec1, vec2, vec3 with forced spilling
<enunes>
no regressions so far
<anarsoul>
ideas is still broken?
<enunes>
yes, since I am unable to cause a failure by introducing spilling to any test with any vec size, I believe the problem with ideas is not spilling
<enunes>
ideas resolves regalloc even with the is_head solution
<enunes>
(and your other MRs applied)
<anarsoul>
:(
<anarsoul>
that's rather big shader and I hoped I wouldn't have to manually walk it through...
<enunes>
well, we can go just trying to fix other issues in smaller piglit tests, one of them might be what is in ideas
<anarsoul>
yeah, likely
<anarsoul>
you can use my r-b and merge this MR
<enunes>
thanks for the reviewing and feedback
<enunes>
we should start merging your other ones too
<anarsoul>
thanks for working on spilling
<anarsoul>
I still need r-b for NIR part
<enunes>
anholt reviewed the phis to scalar one but it's not clear to me if he also meant it for the scalar fcsel as the commits are in the same MR
<anarsoul>
probably not, since I mentioned that it depends on another MR