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<mardestan>
I am unsure as to how good you know the hw details, it is an open card to me. Your programming style and some people talks could refer to that you miss some details, but i am not so sure in that either and depends on who misses them,
<mardestan>
I think for the best results the community committers also, would want to get the details learned, but it can be also that you slightly still troll me.
<mardestan>
Also , have you ever looked into alu electrochematics, do you know what is compounded aka repeated procedures right?
<mardestan>
hardware range checking on source operands zeros in hardware the out-of-range source operands, that means there are no repeated procedures on any of the alus anymore, since one operand is 0
<mardestan>
compound and repeat is not also present in twos complement addition, it just says repetitions are present when you carry or borrow things
<mardestan>
even though divide being heavily compounded, which is why it has a latency longer then on the average other alus
<mardestan>
then when repetitions are not made, it will basically
<mardestan>
quit early
<mardestan>
if you ever were trying to be serious in one of the schools you studied than it would be easy concept to grasp, does not even matter what school it was, i assume international education standards in all of them.
<mardestan>
I for instance do not respect those days, that programmers must be drained with definitely getting higher education, since you can get experience from working on stuff your own, and all the needed bits before that to start doing that, were allready learned from elementary school.
<mardestan>
operation system docs are not neccessary in big parts, cause they do things wrong in most part, however the mentioned dlx pipeling link, is compulsory read sort of.
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<mardestan>
So anything introducing about how hardware does is little more compulsory read then that of all operation system details.
<mardestan>
SO i head to one of the more interesting subjects POSIX part of winnt kernel, and CPU scheduling with scheduler activations.
<mardestan>
I talked about coresight ways to target internal issue queues on in-order processors, and ROBs or reservation stations based issue queues on out-of-order processors
<maciejjo>
hhhhh
<mardestan>
the method to plumb this type of code in
<mardestan>
is with many-to-many scheduler, which is supported by POSIX emulation on winnt type of microkernel, and monolithic kernels all support this in the kernel on some releases
<mardestan>
those are called upcalls, which can be sort of like hijacked to make userspace threads run kernel code
<mardestan>
it is somewhat good, cause you do not have to than author your kernel ddk modules on several platforms, just use allready existing ones
<mardestan>
but it yeah comes with a slight security issue, but even on normal memory based full pipeline mode, that type of scheduling as many-to-many involves or incurs lot of less overhead
<mardestan>
and is by default 1000times faster then the current one used 1:1
<mardestan>
abviously this is seomething hardware vendors would prefer not seeing if we were to tweak old hardware to work out in such pace, but it is how it is.
<mardestan>
by old pal says it is as the best it can be.
<mardestan>
:)
<mardestan>
so by default short pipelined code would work bold millions of times faster, and another 1000fold comes from just using the scheduler, you realise that all hw is massively faster than they claim, and performance problems under any of the hardware should not really exist right?
<mardestan>
so trillion times speed up, toping far beyond the capabilities of human eye, can be got only using a cpu
<mardestan>
gpu would not yet come into play even.
<mardestan>
now the last talks is about cuda/opencl for today
<mardestan>
cuda has such command chain that it allows to not erase queue content and have the subsequent kernel access the queues too
<mardestan>
blum blum shub paper demonstrated it from pseudo-code
<mardestan>
but it exists also of course like they said in both cuda and opencl
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<mardestan>
normally you run cuda kernel on dimensions of blocks on grids of threads
<mardestan>
blocks belong to the same CTA which is scheduled to the very same core
<mardestan>
there are two kernel type of pipelines, asynchronous and synchronous...kernels and cuda streams so to speak
<mardestan>
well streams are inherently async unless you work on the CTA/CORE based of the loop on the same kernel
<mardestan>
however kernels are sequential in respect to each other by default unless you do not use the
<mardestan>
synchronous calls to capture the exception which means the end of the kernel of the first kernel or previous one so to speak
<mardestan>
I did not get this entirely correct, they end up being still sequential, but if you do not end the first shader with a call, you can access the queues from the first kernel
<mardestan>
if you want you can check the confirmation from pixelvault very first public paper
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