Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
kaspter has joined #lima
drod has quit [Remote host closed the connection]
megi has quit [Ping timeout: 246 seconds]
Da_Coynul has joined #lima
Da_Coynul has quit [Client Quit]
nerdboy has quit [Ping timeout: 245 seconds]
nerdboy has joined #lima
nerdboy has quit [Excess Flood]
nerdboy has joined #lima
nerdboy has quit [Changing host]
nerdboy has joined #lima
dddddd has quit [Remote host closed the connection]
megi has joined #lima
dddddd has joined #lima
drod has joined #lima
Net147 has quit [Ping timeout: 245 seconds]
Net147 has joined #lima
adjtm has quit [Ping timeout: 258 seconds]
Da_Coynul has joined #lima
nerdboy has quit [Ping timeout: 258 seconds]
nerdboy has joined #lima
adjtm has joined #lima
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
Da_Coynul has joined #lima
Da_Coynul has quit [Client Quit]
nerdboy has quit [Ping timeout: 258 seconds]
drod has quit [Remote host closed the connection]
jrmuizel has joined #lima
jrmuizel has quit [Remote host closed the connection]
jrmuizel has joined #lima
jrmuizel has quit [Remote host closed the connection]
jrmuizel has joined #lima
sunxi_fan has joined #lima
sunxi_fan has quit [Quit: Leaving.]
sunxi_fan has joined #lima
sunxi_fan has quit [Client Quit]
Da_Coynul has joined #lima
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
<
enunes>
anarsoul: found some corner case bugs on the new spilling code
<
enunes>
can't do the optimization in a few cases
<
enunes>
for example if the spilled reg in load varying
<
enunes>
though maybe this one only reproduced with force spilling
<
enunes>
apparently, also can't store temp and do combine alu at the same time
<
enunes>
and also can't do it for the load portion of spilling a dest register (not ssa)
<
anarsoul>
because load varying stores value to a register
<
enunes>
yeah, and also because load_temp happens after load varying in the pipeline
<
enunes>
so this happened
<
enunes>
load.v ^discard. ^uniform.xyxx, texld.2d 0, load.t -1.xy, mov.v0 ^texture , add.v1 $0 ^v0 $0, sync
<
anarsoul>
"load.v ^discard. ^uniform.xyxx" doesn't make any sense
<
enunes>
uniform is the output of load.t
<
enunes>
so yeah, can't merge the load.t there, need to create a separate instruction before
<
anarsoul>
does it fix ideas?
<
enunes>
dont know yet, am still looking for regressions forcing spilling with piglit
Da_Coynul has joined #lima
jrmuizel has quit [Remote host closed the connection]
kaspter has quit [Quit: kaspter]
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
Da_Coynul has joined #lima
Da_Coynul has quit [Client Quit]
Da_Coynul has joined #lima
<
anarsoul>
enunes: yet I don't understand how "load.v ^discard. ^uniform.xyxx" could happen
<
anarsoul>
we don't support indirect varyings
<
enunes>
anarsoul: it was a bug, dont worry about it
<
anarsoul>
some kind of memory corruption?
<
enunes>
it happened with spilling because the new code merged the load.t and replaced the register with ^uniform
<
anarsoul>
but ^discard is output register here
<
anarsoul>
IIRC we don't support addressing varyings via register yet
<
enunes>
texture needs load.v output to discard to bypass the value to texld
<
anarsoul>
I understand that
<
anarsoul>
but load.v varying index must be constant
<
anarsoul>
not a register
<
anarsoul>
see ppir_emit_intrinsic()
<
anarsoul>
only dest is a register
<
anarsoul>
(or ssa)
<
enunes>
shaders@glsl-fs-copy-propagation-texcoords-1
<
anarsoul>
oh, got it
<
anarsoul>
sorry, still morning for me
<
anarsoul>
I'll go get some coffee
jrmuizel has joined #lima
<
anarsoul>
I just realized that my code to clone uniforms/varyings has a bug
<
anarsoul>
ppir_codegen_encode_varying() assumes that load_coords source is always a reg
<
anarsoul>
but it's not true anymore
nerdboy has joined #lima
nerdboy has quit [Changing host]
nerdboy has joined #lima
<
anarsoul>
I'm surprised it didn't regress in piglit
<
anarsoul>
also I think there's a bug that unnecessarily increases reg pressure for instructions with load nodes
<
anarsoul>
I pushed the fix to my lima-pp-merge-loaduv branch
jrmuizel has quit [Remote host closed the connection]
jrmuizel has joined #lima
ni291187 has joined #lima
ni291187 has left #lima [#lima]
jrmuizel has quit [Remote host closed the connection]
jrmuizel has joined #lima
<
anarsoul>
enunes: did shader-db ever OOMed for you?
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
<
anarsoul>
also it doesn't handle timeouts :(
<
anarsoul>
btw, gpir doesn't handle flt and fge
jrmuizel has quit [Remote host closed the connection]
niceplace has quit [Ping timeout: 244 seconds]
niceplace has joined #lima
jrmuizel has joined #lima
<
enunes>
anarsoul: hasn't OOMd to me
<
enunes>
yeah timeouts are bad
<
enunes>
ppir spilling has an infinite loop bug, you can backport my first patch from the spilling MR
Da_Coynul has joined #lima
jrmuizel has quit [Remote host closed the connection]
jrmuizel has joined #lima
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
jrmuizel has quit [Remote host closed the connection]
Da_Coynul has joined #lima
jrmuizel has joined #lima
jrmuizel has quit [Remote host closed the connection]
drod has joined #lima
<
enunes>
anarsoul: ideas still doesnt work, there is still 1 corner case that I couldn't fix today with multiple forced spilling
tatopopi has joined #lima
<
tatopopi>
Alguien se Lima
tatopopi has quit [Remote host closed the connection]
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
jernej has quit [Remote host closed the connection]
Moiman has quit [Ping timeout: 245 seconds]
Da_Coynul has joined #lima
Moiman has joined #lima
jernej has joined #lima
drod has quit [Ping timeout: 245 seconds]
drod has joined #lima
Kwiboo has quit [Ping timeout: 244 seconds]
megi has quit [Ping timeout: 258 seconds]
drod has quit [Remote host closed the connection]
jrmuizel has joined #lima
Da_Coynul has quit [Quit: My MacBook Air has gone to sleep. ZZZzzz…]
Da_Coynul has joined #lima