ChanServ changed the topic of #lima to: Development channel for open source lima driver for ARM Mali4** GPUs - Kernel has landed in mainline, userspace driver is part of mesa - Logs at and - Contact ARM for binary driver support!
<anarsoul> enunes: I suspect that should fix it:
<anarsoul> I'll check it later tonight
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<anarsoul> yuq825: hi
<yuq825> anarsoul: hi
<anarsoul> we have format description now in mesa
<anarsoul> I asked danvet about it yesterday and he said that panfrost or lima folks should push it
<yuq825> I can not merge this patch which needs a v2 to at least add some comments for their plan, but I can ask in the mail thread for this
<anarsoul> please do
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<anarsoul> yuq825: btw, how did you convince blob to use linear texture?
<anarsoul> looks like we need to RE texture filtering options for linear textures since they don't work. They do for tiled textures though
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<anarsoul> MoeIcenowy: see in src/gallium/drivers/panfrost/ci for details how to build deqp for surfaceless
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<MoeIcenowy> enunes: oh I got some reason
<MoeIcenowy> our current full fb judgement only judges that the scissor is equal to fb
<MoeIcenowy> it thinks the scissor is not full fb if it's bigger than it
<MoeIcenowy> so it's going to send out the bigger-than-fb scissor
<MoeIcenowy> anarsoul: does the spec say what should we do if the scissor is bigger than viewport?
<MoeIcenowy> oh it says "only pixels that lie within the scissor box can be modified by drawing commands"
<MoeIcenowy> so the scissor box can be bigger than viewport, and it should gets clipped
<anarsoul> MoeIcenowy: see comment to MR
<anarsoul> pipe->clear() should clear whole surface
<MoeIcenowy> anarsoul: what will happen if we just try to pass a scissor larger than viewport?
<MoeIcenowy> personally I think the clamping is necessary
<MoeIcenowy> anarsoul: but I will try the rasterizer state fix now
<Tofe> anarsoul: I get for my app the error: "if nir_cf_node not supported"... is it a definitive restriction ? or just not yet implemented ?
<MoeIcenowy> Tofe: GPIR or PPIR?
<MoeIcenowy> if GPIR, there's pending fix for it
<MoeIcenowy> if PPIR, it should had been fixed...
<Tofe> gpir
<Tofe> Damn, there's a fix for everything actually ;)
<MoeIcenowy> we need to collect a `lima-next` branch
<anarsoul|c> MoeIcenowy: mesa should clamp it to FB size for us
<Tofe> MoeIcenowy: if you're talking about "1991" MR, I already apply it locally and it doesn't add "if" to GPIR
<MoeIcenowy> anarsoul: should we depend on this behavior?
<MoeIcenowy> Tofe: yes 1991
<MoeIcenowy> it should kill if nir_cf_node not supported issue...
<anarsoul|c> Tofe: it does
<Tofe> ok I'll check on my side :)
<MoeIcenowy> anarsoul: the rast state fix is not enough to kill state=400000 error on GDM...
<MoeIcenowy> anarsoul: but remove partial clear codepath do fixes it
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<Tofe> ok for the if it's my fault, I refreshed Connor's patch in the wrong way with OpenEmbedded and it screwed up the patch file
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<MoeIcenowy> anarsoul: BTW here it's very easy for lima_bo_create to trigger page alloc fault...
<rellla> fyi, i pushed a lima-next branch ... and now give it a go with piglit
<rellla> ...which doesn't build and needs a fix :)
<bshah> :D
<rellla> done
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<MoeIcenowy> GNOME Shell really do things strangely...
<MoeIcenowy> it clips the screen from part of the FB
<yuq825> anarsoul|c: I can't remember details, but use a EGL extension to import a buffer for rendering can trigger blob render to linear buffer
<yuq825> this extension only exist on some "new" version of blob driver
<yuq825> this is the dump app
<MoeIcenowy> yuq825: ?
<yuq825> gl spec said glclear need to respect scssor
<MoeIcenowy> yes, but gallium says pipe clear() shouldn't respect scissor
<MoeIcenowy> glClear() scissor is dealt at gallium
<MoeIcenowy> `always clears the whole surfaces (no scissoring as used by GL clear or explicit rectangles like d3d9 uses)`
<MoeIcenowy> search "``clear``" in src/gallium/docs/source/context.rst
<yuq825> I see, mesa won't take care this for driver
<yuq825> this is the test for testing the scissor clear
<yuq825> at least AMD GPU do like spec: second draw clear won't clear whole buffer
<yuq825> does your MR get the same result?
<MoeIcenowy> yuq825: according to , mesa emulates scissored clearing by using draw a qual
<MoeIcenowy> I'm still installing git on the test device
<MoeIcenowy> yuq825: oops a part of dump1 is lost
<MoeIcenowy> but of a strange shape
<MoeIcenowy> sorry sent a obvious wrong url -- the latter url is the dump1
<MoeIcenowy> but more strangely
<MoeIcenowy> this is not a regression
<MoeIcenowy> the dump1 is equal to the one generated by master
<enunes> MoeIcenowy: thanks, I'll do some more testing and update my MR based on the comments there, you don't need to submit another MR on the same topic :)
<MoeIcenowy> oh I already sent it...
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<enunes> MoeIcenowy: can we please close it and keep in the original one
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<MoeIcenowy> okay
<yuq825> MoeIcenowy: oh, if mesa did emulate the scissor clear, the result should be same, but the result is indeed not same as AMD GPU
<MoeIcenowy> also not the same with my Intel
<MoeIcenowy> the result should be a triangle is cleared inside, right?
<MoeIcenowy> I'm also facing strange misrendering under GNOME3
<MoeIcenowy> where the dock totally disappeared
<yuq825> send you my dump by mail
<yuq825> did your kernel driver contain the bo wait fix?
<MoeIcenowy> maybe
<MoeIcenowy> I will now upgrade it and test again
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<MoeIcenowy> I forgot whether the kernel build contains the fix...
<MoeIcenowy> I only know my newest build fixes it
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<MoeIcenowy> yuq825: checked the dump, it's the same with my intel
<yuq825> with or without your MR?
<MoeIcenowy> I get the same result on lima both with or wirhout...
<MoeIcenowy> I mean your dump is same with my intel
<yuq825> OK, I miss understand
<yuq825> so let's see if your strange result is due to the kernel bo wait fix
<MoeIcenowy> yuq825: no
<MoeIcenowy> it's not related to bo wait
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<yuq825> I did use this test when implementing partial clear, at that time the result is same as amdgpu with the partial clear and not without the partial clear
<yuq825> how about sleep several sec before read out the pixel?
<yuq825> this result looks like read from in-complete rendering buffer
<MoeIcenowy> yuq825: tried to uncomment glFlush and add system("sleep 1") before and after it
<MoeIcenowy> no change
<MoeIcenowy> I'm going to test with 19.1.0
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<rellla> seems like our shader implementation really goes forward ...
<rellla> maybe this is a good list now to fix the rest one by one ...
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<rellla> btw, is there a way to dump a .png out of piglit per test?
<MoeIcenowy> yuq8251: 19.1-branchpoint is more weird
<yuq8251> 19.1 like not respect scissor clear
<yuq8251> oh, at that time buffer_age is not added
<yuq8251> so buffer won't be reloaded after eglswapbuffer
<yuq8251> you may try to use glflush instead of eglswapbuffer
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<yuq8251> looks like the strange result is due to the scissor rectangle is smaller than expected
<yuq8251> I mean mesa-master result
<MoeIcenowy> what's the possible scissor used?
<yuq8251> the test set the second draw scissor to (w/4, h/4, w/2, h/2), but looks like (w/4, h/4, w/4+16, h/4+16)
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<mardikene193> the last test i did not do, cause that is a bit more complex test
<mardikene193> which finds out , either if simd arbiter wraps around or not
<mardikene193> it's also because that one is in addition to it's importance also considered tricky
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<mardikene193> jrmuizel: I do not know who are you, but there are bunch of latin-americans and spanish who understand that theory quite well.
<jrmuizel> ?
<mardikene193> they did it primarly and exlusively for multi-gpu support
<mardikene193> jrmuizel: they did it absolutely well
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<mardikene193> but I am not 100% sure whether they understand this algorithms-by-block scheduling sucked off to a
<mardikene193> bypass product which is like ""Computing the instructions from queues""
<mardikene193> it is mainly cause they mathematically also present the data who it works, how algorithms by blocks mathematically can be expressed
<mardikene193> Because i would had only written the code, cause i know more about electronechnics than that of math formulas.
<mardikene193> But as a bypass product it collides with ideas of multi-gpu out-order algorithms by blocks execution
<mardikene193> as my implementation is the variation of the rules they express
<mardikene193> mathematically, so i can not be 100percent sure that i am not the only one who quickly knows how to transform those ideas
<mardikene193> it's like math vs. statistics
<mardikene193> my solution involves couple of patterns of statistical analysis
<mardikene193> As i know everything about the code and implementation , i am not very problematic one
<mardikene193> My mission is to defend my estonian boys little as well as big ones
<mardikene193> Similarly thing goes to my countries female subjects.
<mardikene193> To me statical analysis involves Risk Analyses as well as many other thing, and their direct anchestor is Statistical analysis
<mardikene193> in general
<mardikene193> statical/Statistical of course in the first part of the sentence
<mardikene193> I do you an example, if a person gets caught with stealing a skateboard , this is presented as statistical analysis
<mardikene193> and not by theory of likeliness or odds so to speak
<mardikene193> allthough last could be done as subtype of that Generalisation
<mardikene193> Cause the first trigger, is registering the sequence of things that happened
<mardikene193> then also form subtypes of that
<mardikene193> hence Risk analysis, and all others are subtypes
<mardikene193> that what brings me to the theory of khronology, which is the most important subtype of statistical analysis
<mardikene193> allthough it is spelled Chronology in english
<mardikene193> maybe also general philosphy could be the aged term about all of the things
<mardikene193> i really can not comment on the appearance and rank of those subtypes
<mardikene193> more important is that you understand what it is current classification of them
<mardikene193> and current rank also at times
<mardikene193> I am also offended and insulted that such monkeys thought i was insane
<anarsoul> MoeIcenowy: you mean you get alloc failure even with BO cache?
<mardikene193> and the definition of the highest rank about depression for an example IS:
<mardikene193> The outer world and society does not correspond to expectations.
<mardikene193> pretty random filosophical statement which is picked to be on a high rank position in medicine for instance
<MoeIcenowy> anarsoul: yes
<mardikene193> maybe in chronological order thinking can be considered an anchestor of philosophy and everything would be messed up in the tree
<mardikene193> cause that the person owing a capability to think is basically the most importent in human beings world
<mardikene193> owning
<mardikene193> I draw an example
<mardikene193> if MoeIcenowy is capable of thinking every time when he wants to do that
<mardikene193> it is all fine
<mardikene193> If MoeIcenowy is capable deciding whether he wants to think or not
<mardikene193> This is considered to be still very good situation
<mardikene193> HERE noting extra attention: You in plural should all see what the thrill is about
<mardikene193> More closely why the statistical analysis is so high ranked
<mardikene193> cause it is the inhereto/er of thinking
<mardikene193> And about how much you know about Raimond Valgre is subjective the least and rarely met pheonomen as an example
<mardikene193> That a spanish guy threw 108 meters with
<mardikene193> using
<mardikene193> say with less wheighted javel
<mardikene193> this is considered a changing phenomen in statistical analysis
<anarsoul> MoeIcenowy: try commenting out lima_bo_cache_free_stale_bos() call
<MoeIcenowy> but to be honest I think this looks not so dangerous
<MoeIcenowy> the misrendering is a more critical issue
<mardikene193> MoeIcenowy: if you do not know what the issue is, than i perhaps overestimated you...
<mardikene193> :D
<mardikene193> but as i do not know what issue are you talking about
<mardikene193> than unless you are going to present your issue would not know the heck what you talk about
<mardikene193> issue/issue I
<mardikene193> MoeIcenowy: are you powerful?
<MoeIcenowy> no.
<mardikene193> MoeIcenowy: me either
<mardikene193> can you prsent your issue to me, i solve that with 1minute?
<anarsoul> ?
<mardikene193> If we both are thinbking about on-topic programming subjects
<mardikene193> If we are talking about some other subjects or gategory , i may not be able to fill in my promise
<mardikene193> Lots of things in current world can be subjective, and I am not the one that charges you there for it
<mardikene193> It could be the risk analysis showing it is better not to talk with me...
<mardikene193> and i am that flexible that i would not require this too
<mardikene193> The highest rank in planet earth is chronological order of people who can think at the current time
<mardikene193> this is allready a big acheivement
<mardikene193> because when the other subtypes grab a grip
<mardikene193> then they can take the power in charge over
<mardikene193> Why I did not do the last test, might be the question you ask?
<mardikene193> present the live demo on edaplayground how things function
<mardikene193> yeah the answer is: I did not know on first impression and evaluation how to make that quickly during minimal time spent on it.
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<mardikene193> I am a golden boy in many sense
<mardikene193> for me the trust is high ranked
<mardikene193> You need to test me there, if i am able to get motivation to present the data
<mardikene193> when i do science someone robbed me some chanche to do something else
<mardikene193> so everything is so subjective
<mardikene193> variations as scinetists entering our group is also there, as well as the bigger chanche that sportsmen enter into science
<mardikene193> scientists
<mardikene193> so:
<mardikene193> the sensitivity list of in and select of mux_40PARAMB.....
<mardikene193> they state that whenever a new instruction of fetch (bypassed or committed) enters the action
<mardikene193> what happens is that then select is chosen in any way, or that one who enters anyways
<mardikene193> so that instruction takes precedence, in a verilog event based
<mardikene193> So Why it is so:
<mardikene193> ???????????????????????????????????????????????????????????????????
<mardikene193> it asks for a result of assignment in the simd module
<mardikene193> if the writeback was never comitted
<mardikene193> committed
<mardikene193> cause of execution getting a stall in verilog loop, cause of
<mardikene193> the opcode being not recognized, it will wrap around right away
<mardikene193> what happens under the hood is: when simd module do not progress to writeback, a flopped value is offered, which is going to be the same as before
<mardikene193> so in other words, that drives zero to
<mardikene193> issue modules instr_info_table
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<mardikene193> and this one is going to be registered since
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<mardikene193> It involves only linking in the issue module with dummy call though
<mardikene193> errrr.........
<mardikene193> SIMD module sorry from issue
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<mardikene193> what happens honestly is a tricky methof....
<mardikene193> it plays the last element back into simd two times, and the last one is not being registered instead it wraps around
<mardikene193> So yes with 95% likeliness the bets from be is placed into simd arbiter wrapping around
<anarsoul> MoeIcenowy: allocation failure is not good. It's probably not handled properly in lima
<MoeIcenowy> but at least no virtual glitches
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<anarsoul> deqp surfaceless doesn't work for me :\
<MoeIcenowy> anarsoul: I cannot understand why the code even works
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<mardikene193> And it isn't like it is wrapping around fast on it's own, it wraps around with the help of the fetch arbiter
<mardikene193> it is very complex but the simd arbiter and valid bits signals are different
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<mardikene193> I mean buckle your seatbelts while i push down the paddle, but everything will be fine cause everything was meant to be
<mardikene193> this taiwanease guy who made the code, is a hell of a star, but canadians and yanks were even before there
<mardikene193> i am not sure when the generator was made, what suprised me the most, was how russians did their VLIW chips for instance or for an example
<mardikene193> but zwabbit is hell of a big programmer, this guy has a head similar to me
<mardikene193> I offhand do not even remember was he hailing from taiwan or hong-kong though
<mardikene193> in both of the cases his nationality along with the picture proved ethnicity should be chinease
<mardikene193> so to be frank, to demonstrate how simd arbiter wraps around, you need to make instances of 3-4 submodules
<mardikene193> fetch. decode. issue simd alu or starting from decode, 3-5 depending how you call into the simulator
<mardikene193> I of course would prove it rather quick with 20minutes work if someone wanted though
<mardikene193> I have had my own issues in life, but i have capability to think, and generally i am considered ace in the pack even though this is judd trumps nickname
<mardikene193> MoeIcenowy: you wanna present your issue too with scissors in the code or blend, or what is the matter?
<mardikene193> what i tend to think those are fixed function stages minimally configurable
<mardikene193> scissors probably belong to a term called depth testing
<mardikene193> while blending is as it is allready stage name is the same
<mardikene193> i may be wrong, since there is also a viewport transformation which is a stage before depth testing
<mardikene193> so scissors belong either to clipping or depth desting
<mardikene193> while blending is something that happens before the final framebuffer write as middleware stage
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<anarsoul> enunes: are you going to update your MR to drop partial clears?
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