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<enunes>
anarsoul: ah nice, you already included load uniform duplicating in ppir cf?
<enunes>
anarsoul: does ideas work now?
<enunes>
duplicating it like your const patch was exactly how I thought about it too, so looks great
<anarsoul>
enunes: ideas look better but it still fails in regalloc
<anarsoul>
I also have a patch that fuses branch condition into branch, but it makes it even worse
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<anarsoul>
basically it makes no sense to do the fusing if condition is in different block
<anarsoul>
since we have to keep 2 variables live instead of one
<anarsoul>
and it increases reg pressure
<anarsoul>
rellla: I was talking about ppir_reg, create dummy node with ssa dest
<anarsoul>
however it probably won't work...
<anarsoul>
rellla: well, you just need register index from it
<anarsoul>
and it still has to be ssa
<anarsoul>
since it's an ssa :)
<anarsoul>
I'll think about it later
<enunes>
anarsoul: rellla: I wonder if we can just make it read from some pipeline reg?
<anarsoul>
enunes: it doesn't really matter
<anarsoul>
I'd prefer a real reg though since we don't know what's hardware behavior when it uses pipeline reg but instruction doesn't have appropriate unit enabled
<enunes>
rellla: an entire new 'undef' field to be checked for undefined seems like a big overhead just to handle undefs :(
<anarsoul>
enunes: why?
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<enunes>
I don't see why it is so special, and then it needs special handling in regalloc with 'if reg->undef'...
<anarsoul>
enunes: it interferes with no registers
<anarsoul>
so any register can be allocated to it
<anarsoul>
another alternative is to clone it to every successor
<anarsoul>
and then check op in regalloc, and if it's undef (we should probably rename dummy to undef) set live_in to INT_MAX and live_out to 0
<enunes>
anarsoul: shouldnt that be detected naturally with just live_in and live_out not interfering with anyone else?
<anarsoul>
enunes: no, live_in and live_out will be seq of the instruction where it's used
<anarsoul>
it still will interfere with other regs used in this instruction
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<anarsoul>
enunes: idea is to use *any* register for undef and don't increase reg pressure
<enunes>
it can happen that another op is in the same instruction as this?
<anarsoul>
enunes: it's ssa, it can be source of anything
<enunes>
I need to refresh my memory by looking at the example that triggers this
<anarsoul>
out of bounds array reads
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<anarsoul>
enunes: it looks like it's difficult to pipeline load nodes in lower since we don't have information on how it's going to be scheduled yet
<anarsoul>
I have an idea how to do that though
<anarsoul>
pipeline it in lower and then if it's not possible to schedule it in the same instruction create a move for it in node_to_instr()
<anarsoul>
just need to split a helper that creates a move into separate function
<anarsoul>
and then handle load_uniform in ppir_do_one_node_to_instr()
<anarsoul>
(btw it's still not enough to fix ideas)
<enunes>
anarsoul: makes sense, another option would be to always create the ld_uni + move so that it is always schedulable, and have an optimization pass trying to squash everything and remove unnecessary moves
<enunes>
I think eventually we want that kind of optimization pass anyway
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<anarsoul>
enunes: that's what I do
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