02:02 <anarsoul> enunes: with your fixes, nir_lower_phis_to_scalar commented out and fcsel vectorization (I just disabled lowering for now since condition is always scalar) it's able to compile ideas shader

02:03 <anarsoul> rendering is not correct though (lamp colors are wrong) and I suspect that something's fishy in spilling

02:06 <anarsoul> and it spilled only 9 regs which is nice

02:06 <anarsoul> we're doing better than blob!

02:07 <anarsoul> however our shader is twice as long :)

02:07 <anarsoul> 72 instructions vs 36

03:09 <anarsoul> enunes: looks like ppir_codegen_encode_store_temp() doesn't take offset into account for source reg

08:47 <cwabbott> anarsoul: probably some missing NIR pass in the standalone compiler

08:47 <cwabbott> you can try NIR_PRINT=true on the driver & standalone compiler to narrow down what changes it

10:13 <rellla> i'm lost with shader-db :(

10:13 <rellla> i sorted out crashing tests and now it stops proceeding with just stating "Killed" ...

10:24 <rellla> ah... out of memory ...

10:44 <enunes> anarsoul: hmm what do you mean by doesn't take offset into account?

10:45 <enunes> I see that maybe we should use get_scl_reg_index instead of snode->src.reg->index directly, that is probably required

10:45 <enunes> though I just tried that and it didn't fix any tests

10:45 <enunes> ideas works with your suggested changes, but the register indes in store temp codegen doesnt seem to make difference

10:46 <enunes> it seems that we don't use 'register offset' for any of the instructions that have that field so far

15:06 <anarsoul> enunes: "f->temp_write.source = snode->src.reg->index" in ppir_codegen_encode_store_temp looks suspicious

15:07 <enunes> anarsoul: yeah I agree, so I switched that to get_scl_reg_index but that didn't seem to change much, neither fixed any piglit tests

15:07 <anarsoul> enunes: but it's not scalar

15:08 <anarsoul> it's scalar is alignment == 1

15:08 <anarsoul> *if

15:11 <enunes> ok probably need to look at that in less of a hurry :)

15:25 <anarsoul> we also have to make sure that swizzle is sequential for vec2 and vec4

17:48 <anarsoul> enunes: I think you can use ideas to validate your branch with spilling fixes

17:49 <anarsoul> once you get it right lamp should be rendered correctly

19:26 <anarsoul> enunes: I spent some time during lunch to add new nir op for fcsel with scalar condition: https://gist.github.com/anarsoul/cb8caafe22006340b5557f134275f094

19:26 <anarsoul> I'll clean it up tonight and will send an MR

19:45 <anarsoul> however I don't like it like this...

19:46 <anarsoul> I think I'll better replace nir_lower_alu_to_scalar() argument with a callback

22:38 <enunes> anarsoul: yeah I expected the vector fcsel to be implemented in alu_to_scalar instead of a different pass... and I kinda thought that we would just keep the same op and detect the scalar condition by checking the condition swizzle

22:39 <enunes> meh that regression with the spilling change... ideas is a bit too complicated to get right to block the change

22:39 <enunes> I'll likely only have more time now next week