<Ely>
ndufresne: sure I wasn't planning on removing NV12 :)
<ndufresne>
(y)
<ndufresne>
Ely, this will most often apply to encoder, but I think this issue might hit on various stream (the one with special colormetry setup)
<ndufresne>
with uncommon I mean
<Ely>
Alright, hit me up with your 1.12 one liner when you have it, I'll test the other failing files
<ndufresne>
the problem is v4l2, there is no way to enumerate colorimetry, so in gst it had the side effect that an source element that can choose the colorimetry (like an camera isp), would choose one at random, which might not be supported downstream ...
<ndufresne>
oh right give me a minute
<Ely>
No rush, my setup isn't in an easy state to test H.264 anyway, I'm doing some progress on HEVC
<ndufresne>
and there plenty others there that are H264
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<ndufresne>
Ely, the datasheet is intering, there is something called DI_INP_GEN, I don't know myself what it is
<ndufresne>
Ely, but I believe this explains how their tiling works
<ndufresne>
there is bits, for each Y/Cb/Cr to enable "burst size cr: 0 = 24x64; 1 = 32x64; 2 = 48x64; 3 = 64x64"
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<ndufresne>
Ely, so the "endian" thing in the canva I was playing with directly related
<ndufresne>
all these "fifo" have "endian" bit, which apply to the bpp, can that can be 1 2 or 3 bytes per pixels (4 is unused in many placed, means BGRA is not supported everywhere)
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<ndufresne>
page 110 btw
<ndufresne>
that doc is missing a bit of context / prose
* ndufresne
is under the impression they wanted to support big-endian mode ...
<ndufresne>
probably for the onces migrating from mips
<Ely>
ndufresne: The DI_INP_GEN_* registers are used slightly in the deinterlace driver, so I guess DI stands for deinterlace
<ndufresne>
make sense
<ndufresne>
but the same reg comes in VD1_IF
<ndufresne>
-> VD1_IF0_GEN_REG
<ndufresne>
all this seems pretty flexible, but underdocumented ;-P
<ndufresne>
Ely, I was wondering if the transfer from/to the fifo wasn't being made by the same HW
<ndufresne>
Ely, something I notice, is that the AFBC reg are the only one that refers to 10bit
<Ely>
I honestly have no idea
<Ely>
Without AFBC I have no clue about the format you'd get out of the hevc decoder
<Ely>
might even be 8 bit output from a 10 bit input
<ndufresne>
isn't the AFBC an on-the-fly compression ?
<Ely>
yeah it is
<ndufresne>
so the framebuffer itself (the data in DDR) is likely uncompressed
<Ely>
I don't think so
<Ely>
ah
<Ely>
you mean it would only be used in interconnects ?
<ndufresne>
let me ask in-house, if we know anything about AFBC ;-P
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<Ely>
Nah I'm almost certain what's in RAM would be compressed
<ndufresne>
I'm not sure, there is very little dock, and I didn't check the code downstream
<Ely>
AFBC offers random access up to 4x4 pixel blocks
<Ely>
But why would you need random access if it wasn't in RAM
<ndufresne>
yeah, otherwise you don't save any memory bandwidth
<Ely>
also that
<dsd_>
not sure if relevant but when we worked on s905x vp9 decoding, the amlogic decoder was only doing afbc
<dsd_>
but we found a switch to go back to the 'old' format
<Ely>
dsd_: Yeah I think by default they only do that indeed
<Ely>
But in the HEVC driver there is a "double write mode" option
<Ely>
I wonder how this should be supported in V4L2
<Ely>
should it be a buffer flag ? a new pixfmt ?
<dsd_>
didnt measure the throughput other than feeling that 1080p videos were playing satisfactorily
<Ely>
dsd_: With the undef and the double write mode, do you know if the afbc was still written somewhere in memory ? It seems like it's dropped only when double_write_mode == 0x10 ("double write only"), but I'm not sure.
<dsd_>
i suspect its being written twice
<dsd_>
havent explicitly checked though
<dsd_>
for s905x we just got to the point where "it works" but have yet do do detailed testing/polish etc
<Ely>
alright thanks
<ndufresne>
Ely, what do you know about amba/axi, I've seen these acronyme a lot, but never got to the point to understand what this is about
<ndufresne>
what triggers my question is that line "Device port directly to AXI arbitration. No canvas address translation latency."
<ndufresne>
I remember seeing spec where they said the AXI controller was responsible to trigger an ISP interrupt base on the configuration, which was 1 pixel, 1 line, 1 frame basically
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<ndufresne>
ah, that's what ACE means, AXI Coherency Extensions
<ndufresne>
Ely, ah, that was key, now I understand a bit more what HW deal with the endian stuff I have hacked ;-P
<ndufresne>
DMC_CAV_LUT_DATAH
<ndufresne>
Ely, so I guess when they say they are moving away from canva, it means they are moving away from that "translation" which likely adds latency
<ndufresne>
Ely, interesting, venus on DB410c, does not prevent from decoding 4K, it's just slow, but at least I can test the latest patches ;-P
<ndufresne>
Ely, not sure why, but iphone6s_4k.mov works as-is with mainline venus driver
<ndufresne>
haha, never mind, this was ffmpeg being picked, the driver does limit the size
* ndufresne
whished the DB820c was more stable ...
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<Ely>
in what way is it unstable ?
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<Ely>
And so, just to be sure, iphone6s_4k.mov doesn't work right ?
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<ndufresne>
Ely, the USB driver stops working after few minutes, and the decoder break after few tries
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<ndufresne>
Ely, it used to be in better shape, clear there is regressions, or stuff that moved in the kernel and that wasn't yet ported (just rebased)
<ndufresne>
There is a lot of patches in queue for upstreaming still
<ndufresne>
Anyway, I was just unable to test it
<ndufresne>
but I believe the fix I wrote is correct anyway
<Ely>
I'll test today when I need a break from hevc