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<gab>
hi there, anyone familiar with tinymembench on S912 ?
<gab>
I have khadas vim2 boards, and the results for the DDR4 latency on them look worse than an odroid C2 with DDR3
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<Elpaulo>
Hi all. kgdb not work on ttyAML0?
<Ely>
narmstrong: Should the canvas implementation be a device with its own DTS node ? If so, how do you add a dependency in the dts that "vpu and vdec need canvas" ?
<Ely>
I'm asking because I don't know whether the DMC base address should be supplied by the dts to a specific canvas device, or if it should be provided by the vdec/vpu.
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<dsd_>
Ely: ndufresne: unfortunately it seems like the magic NV12 canvas config bit does not work on S805. i guess its a new feature
<dsd_>
i played the same video with and without the magic bit set, and looked at the first 8 bytes of the decoder output for a few select frames. the decoder output does not change
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<Ely>
dsd_: did you also set block mode to linear ? You should | with (7 << 26), and also have blkmode = CANVAS_BLKMODE_LINEAR
<ndufresne>
Ely, did you tried it on your S805 ?
<Ely>
ndufresne: I haven't tried with the endianness modifier, but iirc I did try with blkmode linear and this at least got me the "striped" pictures (https://i.imgur.com/DR1yWOCg.jpg ..)
<dsd_>
i did the 7 << 26, but not linear. trying now
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<ndufresne>
it's possible the bit shifting is a feature of the tetiler
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<ndufresne>
s/bi/byte shifting
<ndufresne>
Ely, we should also verify this on the S905X, will be handy to document the tiling later ;-P
<Ely>
You mean that the endianness modifier doesn't affect the output when in tile mode ?
<ndufresne>
I'm saying we should check if it's the case
<Ely>
yes sure
<Ely>
s/doesn't/may not
<dsd_>
setting linear instead of 32x32 still doesnt make any difference
<dsd_>
and videos still look ok (after going through ge2d pipeline which i havent modified)
<Ely>
dsd_ I guess there's a possibility the first 8 bytes will be the same regardless of the mode though..
<Ely>
and ge2d should adapt with the input canvas configuration so most likely it'll handle it on its own
<dsd_>
i will check more bytes just to confirm that switching from 32x32 does something. but anyway i was hoping the 7 << 26 change to have an affect on the first 8 bytes and it looks like it doesnt
<ndufresne>
the best test will be to use Ely's driver on a S805 to see what it outputs
<Ely>
dsd_: check the picture I linked that does not have the endianness modifier. As you can see, the endianness "reverses" every 8 bytes, but the first 8 bytes are in the right order, regardless of endianness controls.
<ndufresne>
just so we use the same driver, but it's not impossible it's a new feature
<Ely>
ndufresne: Yeah I'll come back to my C1 in the future to test things out.
<dsd_>
oh ok. my ge2d pipeline is definitely swapping things around within the first 8 bytes, but maybe i have my image formats in a muddle. repeating test with full buffers
<dsd_>
i assume looking only at the Y plane is enough here?
<Ely>
yes
<dsd_>
actually i'll take a quick lunch break first
<Ely>
bon appétit
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<dsd_>
Ely: ndufresne: checked a full Y plane buffer. moving from 32X32 to LINEAR indeed affects the decoder output. but then adding 7 << 26 bit has no further effect
<ndufresne>
sad :-(
<Ely>
That would be a real bummer
<dsd_>
i might try your code on S805 anyway another day. would you expect it to be directly testable, or am i going to have to mess with clock setup, DT, etc?
<Ely>
clocks and DT will be ok. Code might have to differ slightly though.
<Ely>
And firmware of course, although I did upload the S805 H.264 firmware to my repo
<Ely>
But I'll take some time in the following days to test on my C1/S805
<Ely>
I'm getting burned out by the HEVC stuff anyway, need to do something else
<ndufresne>
hehe
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