<ssvb>
cptG: how did you build u-boot 2015.01 for your olimex lime?
<ssvb>
and why is it a problem to upgrade to a newer u-boot version?
<ssvb>
if you are trying to use exactly same u-boot binary on lime and lime2, then it's a bad idea
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<ssvb>
u-boot builds are board specific, and the board type is selected at configure time when compiling u-boot
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<wens>
plaes: afaik the codec clocks are still missing?
<plaes>
hm
<plaes>
well, I hope that mripard can take it to his "wip" tree
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<cptG>
ssvb: I had not built uboot myself until a few minutes ago - I relied on the uboot installations on the officical images. The 2015.04 version was from the Arch repo and strangely it works on both boards. BUT it does not boot kernel 3.4.10x, which I'm relying on.
<cptG>
ssvb: but now that you mentioned "building" I went on my working Lime2 system and rebuilt uboot 2015.01 from Arch's PKGBUILDS and took the .bin file from there and now everything works. Strange that the official Lime image does not work for me. Thanks for giving me the helping idea!
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<libv>
has anyone who is involved with sunxi heard of any unbiased creditable open source community figures involved with foxconn or the banana pi?
<NiteHawk>
maybe that weird Taiwanese OSS institute they introduced now? after all they mentioned that a new NPO would be formed
<NiteHawk>
also we'd have to take "foxconn" (group) with a grain of salt. most likely that means kortide?
<wens>
NiteHawk: no, it actually means foxconn
<NiteHawk>
they're really risking their name being dragged into these companies bickering with each other?
<libv>
did anyone hear from foxconn in 2013 or 2014?
<NiteHawk>
i found a few media announcement about bpi that actually mentioned their name back in 2013 / early 14
<wens>
NiteHawk: i think the original idea was they'd design the first version and let others do the work
<wens>
after all, this is a tiny market compared to their normal op
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<libv>
and lemaker went in 7 months from being invited to one of the fighting kids?
<NiteHawk>
wens: probably. but judging from the may 2015 statement they seem to have agreed to get this whole shebang back on track - and so far have failed?
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<wens>
considering there are new boards, i wouldn't say it failed?
<NiteHawk>
wens: i meant foxconn failed to mediate (at least in the way that their previous announcement suggested they would proceed)
<wens>
NiteHawk: right, seems that way. lemaker got the boot
<wens>
the bananapi wikipedia page seems done by them as well
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<NiteHawk>
"them" being who?
<wens>
bananapi vendor
<wens>
don't know which one
<NiteHawk>
you mean sinovoip, or?
<NiteHawk>
looking up whois information for banana-pi.org is telling... that's clearly sinovoip
<libv>
it seems high time that i publically put my foot up the $shit_pi vendors asses, no :)
<NiteHawk>
and isn't it nice they register that domain half a year after the existing bananapi.org ?
<libv>
hah
<libv>
so how much of its original goals has foxconn achieved?
<libv>
yes, they have taken a large part of the market previously mostly covered by cubieboard (which today deserves to have lost that share) and olimex
<libv>
but there's infighting and no credible open source or community story
<libv>
and it all reflects badly on foxconn itself
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<libv>
high time for me to stick the dagger in i guess
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<NiteHawk>
wens: are there additional sources that lemaker really "got the boot", e.g. lost the trademark or something? so far it seems that it's just another round of badmouthing from sinovoip, promising (again) they would take "legal actions"
<wens>
NiteHawk: not really, but they don't seem to be making any new boards either
<NiteHawk>
for now, we probably can't tell. but anyway - how would that fit in with the previous "1. Foxconn insists that Banana Pi should be an open hardware platform, as long as it is used according to its usage guideline, any identity can develop and manufacture Banana Pi related products." ?
<wens>
trademark dispute would discourage others from manufacturing it?
<NiteHawk>
i think only one thing is clear at this point: the facts just don't go together well with the "resolution understandings among all involved parties". i.e. they (whoever that is) don't live up to their 'promises'
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<NiteHawk>
libv: i get the impression that this ominous "FuChu(a)ng OSS Foundation" / "OSS Integral Institute" is the NPO that was to formed. they also show up on whois bananapi.org.tw and whois bananapi.org.cn (the sites mentioned in the agreement from may)
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<NiteHawk>
these people are weird... they're referring to a non-profit organization, and then "BPI team" "slso authorized OSS Integral Institute Co., Ltd. to sell the Banana PI in Taiwan". so this OSS Integral Institute actually is a $shit_pi reseller?
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<focus>
Allwinner A20 has 32K L1-cache?
<NiteHawk>
32KiB (Instruction) / 32KiB (Data) L1-Cache per core
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<libv>
NiteHawk: yeah, more of the same shit
<libv>
it's time that the $shit_pis of this world get a good trashing
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<wens>
NiteHawk: FuChuang was formed in 1999
<NiteHawk>
wens: i see, that's interesting. their domain (dns) records predate the bpi era, so that's plausible
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<focus>
NiteHawk: thanks - any arms out there with a lot more cache? (Intel has 8M L1 cache!)
<focus>
even the ST 200MHz arms are now carrying 4kdata/4k instruction (8K total) L1 cache!
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<focus>
I'm thinking an ARM with 2M to 4M L1 cache should be as fast as any intel CPU out there
<focus>
it would take a power hit - but who cares if its turned on and off on demand (e.g. for gaming)
<focus>
They must run like a 10 year old pentium with that!
<focus>
Fast enough to play doom
<NiteHawk>
i don't think L1 cache size(s) is any useful measure / performance indicator. just for comparison: intel's atom soc family (https://en.wikipedia.org/wiki/Atom_%28system_on_chip%29) seems to feature similar values. i can't give you any real "advice" on alternatives, since i think the pure figure alone is near meaningless
<focus>
NiteHawk, it can be a measure for performance - the L1 cache runs at or near zero wait state of CPU speed, while L2 runs around 15 cycles and peripherals run at 50 cycles, DRAM page change would force DRAM to run at 10Mhz
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<focus>
The core of an application may be 20k to 1M lets say, so if that ran in cache it runs at astronomical speed, but anything that fell off it would run at 10MHz
<focus>
(in approximate terms)
<NiteHawk>
focus: it doesn't concern me, and i can't help you with selecting cpus based on that.
<focus>
OK
<libv>
focus: i am sure that some upcoming 64bit arms will have a bigger set of caches
<libv>
but since when has anyone chose an ARM SoC on the basis of its l1 caches?
<libv>
chosen
<focus>
libv: that would be nice.
<focus>
android stuck at 1 screen because of this problem me thinks
<focus>
not true multi-tasking windows like gnome or fluxbox
<libv>
...
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<focus>
may be someone could ask Allwinner to bring out an A20 with 4M L1 cache :) - defeat intel all over again in the PC market
<NiteHawk>
based on 960mhz clock rate?
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<focus>
NiteHawk: it would run ubuntu at reasonable desktop speeds for bom of $30. Also servers.
<focus>
most laptops would also work properly with ubuntu
<focus>
and not be so sluggish
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<focus>
Not enough L1 cache is a big killer when it come to speed because DDR works at 10Mhz if changing pages all the time
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<focus>
Having more than 2 cores doesn't improve performance (about 4%) because it would cause more page faults. Better to get rid of 3rd, 4th,,,8th core and put in some L1 cache me thinks :)
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<focus>
I guess if i were a rich man, i would buy some arm licenses, and beef up L1 cache to 16M :) and see what happenzzz!
<libv>
...
<focus>
purely for market mischief you understand! :)
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<ssvb>
focus: nobody can make large L1 caches, increasing the size means that the access latency becomes worse
<ssvb>
focus: that's why we have the L1 / L2 / L3 caches hierarchy in modern processors, with each next level of cache trading off some speed for the size increase
<ssvb>
focus: if you try to make a processor with 16M of L1 cache, then you effectively get an equivalent of the modern processors with just L3 cache on board, but no L1 and L2 :)
<ssvb>
focus: and you will definitely not like the resulting performance
<focus>
ssvb: you are right. the only hope is process improvements that leads to scaling that is offering extra speeds and lower power that offers slightly better caches
<focus>
i did manage to work out somewhere that an L1 cache to another L1 cache is better than an L1 + L2 cache - so in that regards, I believe there is still some scope for improvement
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<focus>
I think its something like 15xL1 caches in series is better than = L1 + L2 cache assuming each L1 adds 1 extra cycle to the latency (though I could be seriously wrong!)
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<boycottg00gle>
anybody else had troubles with mainline kernel and soft reset on olinuxino lime2? i see a soft reset _sometimes_ resulting in a shutdown - but atm i can only reproduce with one of two boards :(
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<boycottg00gle>
the only difference i see between both boards is that one is connected via ethernet the other not - but i did receive reports that it happened without ethernet connected, too
<boycottg00gle>
ah - just could reproduce without ethernet as well
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<ssvb>
focus: L1 cache normally has 3 or 4 cycles latency
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<focus>
ssvb: ok - puts all the other calculations off by a factor 4 :(
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<mripard>
plaes: what wip tree ?
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<wens>
rsb v4 series is out, hopefully this one will make it
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