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<ullbeking>
hey guys i have good news about the emmc module on the revived +2E OPi. It's going to be exactly the same chip, but it's going to have android preloaded onto it so yes it will be slower initially but eithe the android bit can be skipped or deleted... hopefully... more details to come
<ullbeking>
do you know anything more KotCzarny ?
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<freemangordon>
mripard: I am trying to load mali.ko on allwinner q8 tablet, linux 4.11.12. All I get is "Couldn't reserve our memory region". I see that error comes from of_reserved_mem_device_init(&mali->dev->dev); in sunxi.c. Is there an example DTS about that /reserved-memory node it needs?
<freemangordon>
plaes: thanks again, that did the job, mali.ko is loaded now
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<PaulR>
hey guys - any pointers to the most stable mainline kernel that includes support for A20 with dual display (lcd & hdmi). I found this branch https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-next . Is this the one or another stable version is available ?
<Wizzup>
MoeIcenowy: did you succeed in trying mesa-lima?
<MoeIcenowy>
Wizzup: nope.
<MoeIcenowy>
It's still too young too simple sometimes naive ;-)
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<Pe3ucTop>
rej: by default UART work from 24Mhz oscilator (and it own behaviour requers 16 clock's) - So in boot mesage you can see it startup with 1.5Mhz base clock for baud generation.
<Pe3ucTop>
rej: And BAUDRATE = BaseClock/N (where N=1,2,3,....) ; so aviable rates are : 1.5M , 750k, 500k, 375k , 300k, 250k, and so on.. There is 115384 which is close to 115200 for stable operation.
<willmore>
Pe3ucTop, do you know if the UART can be clocked from another source?
<Pe3ucTop>
willmore: Yes, it could be clocked from APB whith additional divider.
<Pe3ucTop>
Personaly use (APB 600Mhz)/3 , which result in 12.5Mhz base clock..
<willmore>
Pe3ucTop, how do you implement that?
<Pe3ucTop>
willmore: just changes in DT ..
<willmore>
Ahh, okay. So, the serial drive will adapt?
<willmore>
What's the max divider?
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<willmore>
IIRC it's 16 bit.
<willmore>
but it's been a long time since I looked at the 8250
<Pe3ucTop>
willmore: I did not check , may be 16 or 32 bit..
<Pe3ucTop>
16 bit by datasheet.
<willmore>
Pe3ucTop, thank you.
<willmore>
Even at 12.5MHz base, it's still plenty accurate for low baud rates. Seems like it would make more sense to use this higher speed by default.
<willmore>
It would help the driver provide more odd baud rates like the crazy one used by the esp8266 modules.
<rej>
Pe3ucTop: Thanks, but it does look like it's running at ~760kHz when I set it to 921k6.
<Pe3ucTop>
rej: 750k probably.
<rej>
Yes, it varies a bit. The point is that it's way off.
<Pe3ucTop>
rej: way off off ?
<willmore>
That's the best the driver can do with a base clock of 1.5MHz.
<rej>
Like 20% away from what it should be.
<rej>
So that makes the UART (or all of them I guess) unfit for high baud rates?
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<willmore>
rej, with the default base clock, yes.
<willmore>
Even at 12.5MHz, you're going to have a lot of error at 921k6 because that's in the middle of two divisors. You can have 961k5 or 892k8
<willmore>
Pe3ucTop, can you set a different divisor from APB? I.E. How fast can you clock that thing?
<Pe3ucTop>
willmore: yes, with 12.5M base most rates are useless, even 115xxx have bigger error..
<willmore>
Pe3ucTop, at 12.5M base, 115200 is only off <1%
<willmore>
It'll get better at 18.75 if that's possible.
<willmore>
921k6 gets closer at 937k5
<Pe3ucTop>
willmore: when I played with clocks, I got UART initialized from APB 600Mhz without divider the base rate 37.5Mhz but it was unstable (crashing and so on)... 18.75 did not tried - useless for me.
<willmore>
The design of the 8250 should easily tolerate 6% or so clock error.
<willmore>
Pe3ucTop, understood. What speed did you need?
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<Pe3ucTop>
that meet 50M/x , so 12.5M was perfect for me...
<willmore>
K
<rej>
I am not sure how to set that clock. Assuming I need to do it through FEX.
<rej>
It probably wouldn't be the only thing I need to change.
<rej>
I still don't get why the clock wouldn't be simply set to fit UARTs (115k2 * 8 = 921k6) to begin with.
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<willmore>
rej, because the clock is generated through division, not multiplication.
<willmore>
921k6 is a very strange baud rate. There is only one common xtal frequency that generates it.
<Pe3ucTop>
rej: because each device have own clock it work from and when those are not equal there is error in communication.
<willmore>
And these inexpensive SoCs use common xtal frequencies for cost reasons--and they need to provide clocks for dozens of different subsystems.
<Pe3ucTop>
as willmore say, whith dividers on both sides we need to find rate which is good for both (equal).
<willmore>
Or at least minimizes the error.
<willmore>
Looks like <3% is the prefered value, though 6% should be enough.
<rej>
I'll look elsewhere for a solution, then. Thanks!
<wens>
Net147: you missed the last bit about "clk rates not guaranteed"
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<Putti>
wiki admin: can cloudflare email protection be disabled from the wiki? I don't think many people have emails there and it makes it difficult to see clock rates and stuff that are marked with the @ symbol.
<L29Ah>
hi, i'm trying to get smp working on a20 on mainline-rt w/ unmodified cubieboard2 dtb and minimally modified defconfig; cpu1 doesn't get up at boot (dmesg: http://bpaste.net/show/d09eedea5326)
<L29Ah>
-bash: echo: write error: Function not implemented
<L29Ah>
what could be wrong?
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<sunxi_fan>
BTW with this dual head kernel, i have to investigate two corner cases i'm falling into..
<sunxi_fan>
1. if the uboot is simpleFb enabled, the kernel at boot crashes with a Null pointer exception
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<sunxi_fan>
2. if the uboot is "dumb" (no simpleFb, of couse view log on serial..) and the kernel boot with Hdmi Tv set connected, again NULL pointer exception..
<sunxi_fan>
of course it was smooth as silk, if i have "uboot dumb", boot kernel with only internal LCD, then i connect the tv set on HDMI .. that's ok!
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<wens>
L29Ah: smp depends on u-boot providing PSCI
<wens>
a new mainline u-boot
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<L29Ah>
uh oh
<L29Ah>
thx
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<willmore>
Putti, enable javascript and that goes away--IIRC.
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<Putti>
willmore, sure but the code is not free
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<ullbeking>
I need to ask a few detailed questions about +2E. Probably mailing list is better format. Are our mailing lists any good?
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<willmore>
Putti, I'm not sure what you mean. If you enable javascript on the wiki, the email hiding for the screen resolutions goes away.
<willmore>
It's a bug.
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<Putti>
willmore, I meant the JS is not free and because of that I don't want to enable it.
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<Putti>
Which one to choose for audio codec device tree node with H3 TV Box: LINEOUT, Speaker or Heaphone? I tried all of them and the sound is really low in all of them so I guess it doesn't really matter on that part. The audio jack is together with CVBS so LINEOUT sounds the best option for me. Do you agree?
<Putti>
the binding I'm talking about is the one documented in Documentation/devicetree/bindings/sound/sun4i-codec.txt
<L29Ah>
i wonder if i can chainload u-boots easily
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<ullbeking>
Putti: i'm just jumping in really naively with no context, but why not ogg/vorbis?
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<Putti>
ullbeking, I tried "speaker-test -twav -c2" as documented in the wiki, and also with the Android OS loaded by the manufacturer the sound volume was low. So it could be just how the hardware was designed.
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<ullbeking>
Putti: i had no idea what i was suggesting there, it just seems like a worthwhile thing to try
<Putti>
ullbeking, ah right, so you think it could be some problem with the driver. I will definitely try that.
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<Putti>
ullbeking, When I select in alsamixer "Mono Dif" the volume is quite high, at an level that you would probably normally expect. But when "Stereo" is selected the volume is very low.
<ullbeking>
Putti: i think you think i know a lot more than i do
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<buZz>
Putti: mono audiosignals played over 2 speakers are 2x louder than different signals played on same volume on 2 speakers
<buZz>
this is why those 90s rave soundsystems always used mono setups ;)
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<buZz>
or probably less than 2x , but still signifantly louder
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<Putti>
interesting!
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