<KotCzarny>
i think montjoie might be able to answer that
<montjoie>
I do not know well gmac on A20
<KotCzarny>
isnt it served by the same driver as the one in h3?
<montjoie>
no
<montjoie>
its dwmac-sunxi not dwmac-sun8i:)
<KotCzarny>
ahm
<montjoie>
A TRAP!
<KotCzarny>
sun7i-dwmac even
<KotCzarny>
(at least in 4.9)
<montjoie>
as I read the mail, its clearly a pinctrl problem (out of my knowledge)
<tkaiser>
guest2: If you work on something for R40 you're pretty much out of luck anyway. Either choose the 'legacy combo' https://github.com/dan-and/BPI-M2U-bsp or use both mainline u-boot and kernel (and be prepared that not much will work)
<montjoie>
the filename is dwmac-sunxi.c but yeah the modulename is sun7i-dwmac
<wens>
The A20 has the GMAC (dwmac-sun7i) and EMAC (sun4i-emac), and it's possible to route them to different pins
<wens>
the "shared clock" thing is bogus
<tkaiser>
wens: Why?
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<guest2>
In case of uboot-sunxi - can I increase in the linker script the amount of SRAM memory for .sram section without any side effects?
<wens>
tkaiser: nothing is shared, so I have no idea what he's talking about
<wens>
unless you count the ahb bus
<tkaiser>
wens: Ok, maybe some sort of 'people love simple explanations/excuses... even if wrong' ;)
<tkaiser>
'We did not figure out how to do it' sounds differently :)
<wens>
the EMAC pins do conflict with commonly used GPIO pins, so one has to reserve them when doing the design
<wens>
and about the A64 PMIC, I believe regulator support is in
<wens>
MoeIcenowy is the main (and possibly only) person pushing A64 support
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<tkaiser>
wens: Unfortunately for an A64 laptop there is a bit more to consider than basic PMIC support. Most important one: prevent things catching fire (battery charging logic)
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<wens>
MoeIcenowy has something in the works
<wens>
my A64 boards are still lying around, untouched and unused
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<tkaiser>
I know but still... and Olimex' laptop wouldn't sell anyway with just 1GB DRAM and being too expensive...
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<tkaiser>
wens: Let's see what Tsvetan has to answer to your rectification :)
<KotCzarny>
best comment from olimex:
<KotCzarny>
For all our further boards we will be conservative and make boards only when we see good linux support.
<KotCzarny>
When we started the laptop A64 was relatively new chip. We were ready with the hardware approx one year after we started, but A64 user experience was worse than A20 for almost one more year which prevent us to release the laptop! This is what happens when you use new chips with missing Linux support, you can make toy running Android but nothing which you can actually use with Linux
<wens>
*sigh
<Wizzup>
eh
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<Pe3ucTop>
Hello, could anybody comment on "sunxi-nand-image-builder" , question about scramble data - what for it is used ? Could data scrambling be excluded for --boot0 generation ?
<Pe3ucTop>
also - is one copy of boot0 block is enough or all N-copies must be present ??
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<Pe3ucTop>
Also - is there posibility to dump BROM and check for eGON parameters it looking for ??
<tkaiser>
wens: I believe you and him are using the term 'clock' with different meaning anyway... and for me personally the attempts to use EMAC+GMAC in parallel comes a bit (too) late now
<wens>
tkaiser: he's referring to the external RX CLK from the PHYs, which Stefan's email actually mentions
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<KotCzarny>
brief process tag thread raw time threadtime long
<KotCzarny>
oops.
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<MoeIcenowy>
KotCzarny: SODIMM have 64-bit data lines
<MoeIcenowy>
but embedded memory controllers are nowadays usually 32-bit
<KotCzarny>
64bit chips use the same mem controller or are closer to year 2000 already?
<MoeIcenowy>
wens: I think according to mikey from sinovoip, their experiments on dual-MAC A20 failed
<MoeIcenowy>
KotCzarny: yes
<MoeIcenowy>
or sometimes dual-channel 32-bit
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<MoeIcenowy>
but dual-channel 32-bit still cannot fit SODIMM as SODIMM is designed for single-channel 64-bit
<KotCzarny>
it's a pity. also from mem bandwith pov
<MoeIcenowy>
e.g. A31 (without s), A80, RK3399 uses dual-channel 32-bit
<beeble>
why? dual 32bit controller makes more sense for such a platform then a single channel 64bit
<MoeIcenowy>
P.S. there's something to mention: LPDDR3 chips are usually directly 32-bit, and as some LPDDR3 are designed to PoP, the SoC must have also 32-bit memory controller
<beeble>
KotCzarny: don't compare a x86 machine with multirank multichannel 64bit with a soc targeted for embedded
<KotCzarny>
ahhum.
<KotCzarny>
so we would never see such option.
<MoeIcenowy>
some vendors make special 32-bit SODIMMs
<MoeIcenowy>
for embedded
<MoeIcenowy>
but they'
<MoeIcenowy>
they're usually specially tagged as "customized" or "embedded"
<wens>
MoeIcenowy: sounds like something was routed incorrectly
<MoeIcenowy>
there's a document called "IDT_79RC32438_APN_20031029.pdf" which mentioned some possibility to use 64-bit DRAM on 32-bit controller
<MoeIcenowy>
It's part of the application note of the IDT RC32438 chip
<MoeIcenowy>
P.S. it seems that board vendors now start to use LPDDR3 on AW chip designs
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<MoeIcenowy>
for example, recent Pine family boards and the Orange Pi 3 Plus board use LPDDR3
<MoeIcenowy>
and memory bandwidth is also going to be a problem on these chips, as they now adds 4K support to these hardware codec
<beeble>
MoeIcenowy: muxing the datalines as described in that appnote for ddr3 is a bad idea. you will have a lot of fun adapting the timings. after you found muxes fast enough and placing/routing them in the layout
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<wens>
plaes: minor issue about the a10/a20 ccu driver
<wens>
plaes: you force ahb to use pll6 as it's parent, but the list of parents for ahb for a20 doesn't have them
<wens>
hmm, it's just the comment that's misleading
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<paintenzero>
montjoie: Do you have all cpu cores online? The problem is I have only 1 core available on any 4.x kernel I compiled :( How do you make your kernel run all 4 cores?
<MoeIcenowy>
paintenzero: what SoC
<paintenzero>
MoeIcenowy: Allwinner H2+
<MoeIcenowy>
please check your u-boot
<MoeIcenowy>
and boot mode
<tkaiser>
paintenzero: especially if you used before legacy kernel with same config :)
<paintenzero>
MoeIcenowy: could you please tell what should i check? :)
<MoeIcenowy>
your boot.scr
<paintenzero>
MoeIcenowy: but what should i change?
<MoeIcenowy>
check if it sets bootm_boot_mode
<MoeIcenowy>
if it's set, change the value to "nonsec"
<MoeIcenowy>
to boot legacy kernel it should be "sec"
<paintenzero>
hmm, I don't have any bootm_boot_mode
<paintenzero>
and the legacy kernel is booted ok with it :/
<MoeIcenowy>
what's your u-boot version
<MoeIcenowy>
if legacy kernel boots ok, mainline ones will be not ok ;-)
<paintenzero>
oh, pardon me! I do have bootm_boot_mode=sec. I will try to change it
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<paintenzero>
Yeah, it is working! Thank you!!
<sr-digitronic>
Are there any known issues with combination of A20, LCD, mainline U-Boot and legacy kernel? I try to display a bootlogo with 2017.07, but as soon as linux starts, the lcd output gets corrupted
<MoeIcenowy>
it's normal ;-)
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<sr-digitronic>
does that work beter with mainline linux, does that even support LCD? (I do not understand the matrix in the wiki completely)
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<guest2>
Hi
<guest2>
I'm trying to write simple bare-metal app for Allwinner R40 which should generate some messages via UART0, and I noticed ind pdf doc that there are 3 registers with the same offset 0x0:
<guest2>
UART_RBR, UART_THR and UART_DLL
<guest2>
is this some kind of misprint in doc?
<guest2>
How 3 registers can have the same offset?
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<guest2>
Maybe the role of this offset 0x0 is changing depends on some other settings?
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<freemangordon>
KotCzarny: you were right, thanks, USB OTG needs at least one gadget loaded
<wens>
guest2: the description already says what conditions it is valid, in blue text even
<freemangordon>
Wizzup: parazyd: ^^^
<wens>
guest2: and it's really just a standard 8250 UART
<Wizzup>
freemangordon: why do you put it otg though?
<Wizzup>
Don't you want it in host mode?
<freemangordon>
Wizzup: no
<Wizzup>
ok
<freemangordon>
1st - this is the default
<freemangordon>
2nd - I would like to be able to expose it as mass storage. Some day :)
<Wizzup>
I usually just set dr_mode="host" and also set the driver to host in the kernel. I guess for charging that's a pita
<Wizzup>
exposing it as mass storage is pretty simple actually
<freemangordon>
while being a host?
<Wizzup>
no
<Wizzup>
:)
<KotCzarny>
fmg: you can still leave it in otg mode (which will detect what is connected)
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<KotCzarny>
though i haven't tried how well it works
<Wizzup>
if you use an otg cable it should be ok
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<Net147>
asyring: not sure as I have been busy with other things. I think plaes was going to pick up and continue the work.
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<camh>
felboot can use a uboot boot script or uEnv environment text file. Is it possible to use a binary environment file in the same format as written to an SD card?