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<oliv3r>
Hi, i'm playing around and trying out some things, but i'm getting stuck on 'proper module loading order'. In essence, I have a module, that requires a clock to be running from a nother module. So i have the clk_prepare_enable(clk_get_parent(clk)) step in my probe function. However, that only works if the parent clock provider is already loaded. Sadly, the clk_prepare_enable(parent_clk) does not probe/load/enable the
<oliv3r>
clock if the module is not loaded yet. How can I get parent supplying module to be loaded? I do have a reference in the device tree setup as well using clocks = <&parent 0>;
<oliv3r>
(parent only has 1 clock)
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<mripard>
oliv3r: call clk_get
<mripard>
and check your return code
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<oliv3r>
mripard: yeah i'm changing it to devm_clk_get right now, but i was under the impression (assumptions and all that) that clk_get_parent would sort out the details :)
<wens>
nope
<oliv3r>
so i'll ask the hw_clk what the parent_name(s) is, and then clk_get on the parent_name
<oliv3r>
btw, any of you went to FOSDEM?
<oliv3r>
i missed it ;9
<oliv3r>
well wasn't able to
<mripard>
but why are you doing that
<mripard>
call clk_get, clk_prepare_enable on the clock
<mripard>
done.
<mripard>
you don't need to take care about the parent at all
<wens>
oliv3r: when you call clk_get, what you get is <&parent 0>;
<wens>
so it would return -EPROBE_DEFER if it's missing
<wens>
why would you call clk_get_parent anyway
<oliv3r>
which i can then return to the caller which would sort things automagically
<oliv3r>
well because I want to 'enable' the parent clock :p so clk_get_parent sounded like what i needed
<wens>
try actually reading the API docs, instead of just guessing
<oliv3r>
i find the clock docs to be very light on details
<oliv3r>
i still have them open, so i'll re-read them again
<oliv3r>
maybe i did missunderstand something
<mripard>
maybe because you're overthinking it ?
<oliv3r>
quite likley
<mripard>
it really is just as simple as calling clk_get and then clk_prepare_enable
<oliv3r>
alright, i'll dig into it
<oliv3r>
thanks you guys
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<oliv3r>
hmm i did forget to specify that my module does create a clock, and thus the clock'd get would be the parent of the clock i create, maybe that's where the confusion comes from on my end
<wens>
blah, it's 7 degrees outside, raining, and no indoor heating x_x
<oliv3r>
and clk_register does a few things with the parent via the init data
<wens>
the clk framework matches parents by strings, _without_ checking for ordering
<wens>
if it's not there, the newly registered clock is orphaned, until that clock is registered
<wens>
I suppose the clk provider is supposed to deal with this, by verifying that the parent is actually there
<mripard>
and you still don't have to enable the parent clock in this case
<oliv3r>
so my clock does it's setup, names the parent clocks in the init table and registers itself, so that when a user of my clock does the clk_prepare_enable() step, it enables all of the clocks int he chiain? my_clk->parent_clk->its_parent etc ...
<oliv3r>
because that right now is not working :)
<wens>
it should
<wens>
but if it was orphaned when it was enabled, the still-non-existent parent won't be enabled
<wens>
that is why you need to deal with ordering in your code
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<embed-3d>
Mr__Anderson: xerpi: willmore: The right channel for PVR talks would be #powervr. The biggest Problem on those Series5 and Series 5XT GPU (SGX5xx) is the leaked code.
<embed-3d>
This is the reason, why I didn't spent much time on this during the last moths/weeks. And mainlinig is nearly impossible with the current situation...
<embed-3d>
_BUT_: How can I prove that those informations come from reverse engineering and not from the leaked legacy code?
<embed-3d>
Small example: The SGX gpus have an autoclocking feature, for each clock the register is 2 bit wide--> conclusion and testing: 0x0 off, 0x1 on and 0x2 auto.
<xerpi>
embed-3d, why do you need to prove that this info comes from RE and not from the leaked code?
<xerpi>
in order to be able to mainline the code?
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<KotCzarny>
xerpi: because patent trolls?
<xerpi>
patent trolls?
<KotCzarny>
you know, the ones that bully everyone around with lawsuits
<Ke>
patents are supposedly public, you should never have to reverse engineer to get their contents
<Ke>
I reality of course, perhaps...
<KotCzarny>
did you hear about free-electrons case?
<KotCzarny>
they have to change the name because.. word 'free' was trademarked in france
<montjoie>
yes
<embed-3d>
xerpi: The leaked code is proprietary closed source! And the license doesn't allow this!!!
<xerpi>
yeah but then it's "impossible" to prove you haven't looked at the leaked code :/
<embed-3d>
xerpi: That's the problem!!!
<wens>
so it's basically dead
<wens>
unless they themselves open the stuff up
<KotCzarny>
hehe, leaked on purpose?
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<embed-3d>
I'm trying since a few moths to move Img Tech to release their leaked code under a opensource license, but they don't want to move....
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<wens>
a) they don't own the copyright b) they don't want to spend the time to clean it up
<xerpi>
yeah seen your tweets
<wens>
IIRC b) was a factor back when open source drivers were discussed for Series6
<embed-3d>
Img Tech: "We continue to review the options to determine the benefits of an opensource driver but at this point in time we do not have the resouces for this."
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<KotCzarny>
or in other words, the only person that wrote their drivers is either busy or fired already and no one wants to touch that stuff again
<KotCzarny>
;)
<wens>
:)
<embed-3d>
:)
<wens>
embed-3d: any chance they could provide tips for porting series6 driver to other platforms?
<KotCzarny>
in that light we should be happy that aw hired wink to at least work on docs
<embed-3d>
wens: I don't think so. Porting Series6 "opensource" driver to be able to work with mainline should be possible. I allready started this but this gets very fast very ugly!!!
<embed-3d>
But the most initialization is done via user space librarys ...
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<montjoie>
wens: I still hit the problem with A83T and unusable packet loss ethernet and since I am not the only one to hit it, any idea on how to fix it ?
<wens>
montjoie: no idea, as I'm unable to reproduce it
<wens>
montjoie: does your board have a revision number?
<montjoie>
wens: will check it after work
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<xerpi>
embed-3d, actually, SGX is one of the components I care less about of the Vita SoC
<xerpi>
I'm more interested in understanding the display engine and DSI blocks
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<junnie>
Is anyone using sopine A64? I just got a board and do not know how to flashing eMMC with FEL. Because u-boot does not build u-boot-sunxi-with-spl.bin for sopine64, so I only have spl for test.
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<oliv3r>
wens but the dt 'creates' the ordering no? i mean i set the parent clock via the clocks attribute? the code doesn't know what other module it needs
<oliv3r>
and thus i'd need to still call clk_get()
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<oliv3r>
ah, looking at others, clk = clk_get, followed by __clk_get_name(clk)
<junnie>
hanni76: I see atf is /dev/null in u-boot.its. So I suppose it is not needed for non-secure case. Did you run "sunxi-fel uboot u-boot-sunxi-with-spl.bin" to boot uboot?
<hanni76>
junnie: no , I never used fel
<hanni76>
junnie: i think atf is always needed for a64 (i may be wrong)
<hanni76>
junnie: at least you can't build latest u-boot without atf
<junnie>
do you use sopine board? It does not support uSD card. So I have to find a way to burn eMMC.
<hanni76>
i am using nanopi a64, it is very similar
<junnie>
Thank you very much!! I had thought it is a big crystal. I had never see so mall slot.
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<montjoie>
jernej: do you have retested your bpi M3 for the ethernet problem ?
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<jogoes>
Hi! Hi got a Parrot board v1.1 with A33 R16, and I would like to get a demo .img file to flash it with Phoenix tools. Anyone knos where could I find one of those images? Thanks in advance!
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<KotCzarny>
one usually goes to vendor for vendor images
<KotCzarny>
this channel is about freeing allwinner socs from crappy closed code
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<KotCzarny>
which means people build their own systems here
<miasma>
jogoes: hi, are you one of the scala guys
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<jogoes>
Hi
<jogoes>
No Im not
<jogoes>
I expect to build my own system
<jogoes>
but I have no image to start
<jogoes>
just to see it working
<jogoes>
and then I´ll make a step further
<miasma>
the original vendor images might not be good for customizing
<miasma>
but you can test the hardware works
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<tkaiser>
jogoes: If you struggle with Phoenixcard (crap IMHO) you might give a random Linux image with mainline kernel a try and exchange .dtb (overwrite with sun8i-r16-parrot.dtb)
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<embed-3d>
montjoie: I've tested bpi M3 (current mainline) yesterday, I had to disable the wifi and and wifi_powersequence due to a current bug with ac100/clocking, but I don't see your ethernet problem.
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<embed-3d>
montjoie: v1.2
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<montjoie>
embed-3d: so your ethernet is stable and with good bandwith ?
<embed-3d>
but I have some problems with my power connector/power supply ...
<embed-3d>
sometimes my board turns of and then I had to rotate the connector till the power is back ...
<embed-3d>
montjoie: I don't have any problems there. What for a switch do you use? I can do some load tests on wednesday and try to reproduce your problem. What do you do/see exactly when you have those problems? (a log would be helpful)
<embed-3d>
montjoie: Do you have also a boot problem with latest mainline?