#linux-sunxi on 2018-08-15 — irc logs at freenode.irclog.whitequark.org

2018-08-03 10:18 rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*

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13:54 <jernej> MoeIcenowy: ping

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14:08 <MoeIcenowy> jernej: pong

14:09 <jernej> MoeIcenowy: Did you manage to test my yesterday's suggestion?

14:09 <MoeIcenowy> what?

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14:09 <MoeIcenowy> (my brain gets desycned

14:09 <MoeIcenowy> desynced *

14:10 <jernej> it was for undetected monitor at boot

14:10 <jernej> let me find it

14:10 <MoeIcenowy> jernej: btw for the exclusivity problem. without it on A64 when booted with the WaveShare screen connected, it cannot work

14:11 <MoeIcenowy> because TCON0 become 48MHz (should be 32MHz

14:11 <jernej> https://irclog.whitequark.org/linux-sunxi/2018-08-14#22830517;

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14:11 <jernej> ah, that problem

14:11 <jernej> I didn't discover the root problem

14:12 <MoeIcenowy> jernej: undetected monitor is not a problem at all

14:12 <MoeIcenowy> because hpd will soon be ok

14:12 <MoeIcenowy> automatically

14:12 <jernej> anyway, both TCON0 and HDMI phy clock can be set to 32 MHz, so I don't know why it gets set to 48 MHz

14:12 <jernej> what do you you mean by "will soon be ok"?

14:12 <MoeIcenowy> jernej: btw I think U-Boot sets sth to 128MHz

14:12 <MoeIcenowy> jernej: after several msecs

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14:13 <MoeIcenowy> the state will come from disconnected to connected

14:13 <jernej> well, it's not right either

14:13 <MoeIcenowy> and I cannot reproduce this any longer

14:13 <MoeIcenowy> and this is not the key lead to the problem I found

14:14 <jernej> but yes, A64 doesn't have lower PLL limit set to 192 MHz, so with 128 MHz there might be issues

14:14 <MoeIcenowy> the key is U-Boot seems to drive the PLL to high

14:14 <MoeIcenowy> jernej: this is not the key, pll is 256MHz when booting

14:14 <jernej> wait, is it 128 MHz or 256 MHz?

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14:20 <MoeIcenowy> jernej: I cannot remember the clock tree accurately

14:20 <MoeIcenowy> but the kernel is definitely misbehaving

14:21 <MoeIcenowy> as theortically it should CLK_TCON1 = CLK_HDMI = CLK_HDMI_PHY = 32MHz

14:21 <MoeIcenowy> no one should be 48MHz

14:22 <jernej> exactly

14:22 <MoeIcenowy> add the exclusivity surely fixes this

14:22 <jernej> I think I noticed that modes read from EDID contained 48 MHz rate at one point

14:22 <MoeIcenowy> what?

14:22 <MoeIcenowy> I think the EDID has only one mode

14:23 <jernej> well, I don't know where it come from

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14:23 <MoeIcenowy> jernej: EDID fails and 1024x768 is chosen?

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14:24 <jernej> but I suggest you enable DRM debug info to see if 48 MHz by any chance comes from mode setting

14:24 <jernej> maybe

14:24 <MoeIcenowy> `mode: 0:"1024x600" 43 32000 1024 1064 1112 1152 600 613 616 645 0x48 0xa`

14:24 <MoeIcenowy> I enabled it

14:24 <MoeIcenowy> and no chance

14:24 <MoeIcenowy> everywhere says 32000

14:24 <jernej> what if you disable exclusive rate patch?

14:25 <MoeIcenowy> exclusive rate patch doesn't change the behavior of DRM subsystem

14:25 <MoeIcenowy> it only changes behavior of clk fx

14:26 <jernej> can you add debug output to all places where clock is set in TCON, HDMI and HDMI PHY clock?

14:26 <jernej> I could swear that driver got 48 MHz input from somewhere

14:27 <MoeIcenowy> no it's impossible.

14:27 <MoeIcenowy> the dotclock is surely 32000

14:27 <jernej> well, that 48 MHz must come from somewhere

14:28 <MoeIcenowy> jernej: come from not exclusive

14:28 <MoeIcenowy> not exclusive clocks are possible to be effected by other clk_set_rate

14:28 <jernej> exactly, but not if all set same rate

14:29 <MoeIcenowy> jernej: but they have different parents

14:30 <MoeIcenowy> oh not it's tcon0, not 1

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14:41 <MoeIcenowy> jernej: the clk_set_rate call in sun8i_dw_hdmi_encoder_mode_set and sun8i_hdmi_phy_config are all 32000000

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14:43 <jernej> what about TCON's?

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14:47 <MoeIcenowy> in sun4i_tcon_mode_set tcon->sclk1 is set to 32000000

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14:47 <MoeIcenowy> jernej: ^

14:48 <jernej> hm... now I'm confused

14:48 <MoeIcenowy> it's surely the fault of CCU

14:48 <jernej> anyway, you are experimenting on A64, right?

14:49 <jernej> I noticed similar issues on R40

14:49 <MoeIcenowy> yes

14:51 <jernej> I guess I have to debug it a bit

14:52 <jernej> I want to know why it gets 48 MHz

14:52 <jernej> I mean what sequence of commands leads to that

14:52 <MoeIcenowy> jernej: pll-video0 = 128MHz, hdmi (tmds) = 128MHz, tcon1 = 32MHz

14:52 <MoeIcenowy> when booting

14:52 <MoeIcenowy> (before drm

14:52 <jernej> yeah, that should be 192 MHz

14:53 <MoeIcenowy> after booting pll-video0 = 192MHz, hdmi-phy-clk = 32MHz, hdmi = tcon1 = 48MHz

14:53 <jernej> doesn't TCON set exclusive rate?

14:53 <MoeIcenowy> I think TCON is exclusive

14:53 <MoeIcenowy> but HDMI & HDMI PHY is not

14:54 <jernej> I'm not really happy about this exclusive mode

14:54 <jernej> since at least in single monitor setup

14:54 <jernej> it should work without it

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14:55 <MoeIcenowy> when hdmi-phy-clk joins

14:55 <MoeIcenowy> I think it's the problem

14:55 <MoeIcenowy> as he remains 32MHz

14:55 <MoeIcenowy> when hdmi and tcon1 is trapped into 48MHz

14:56 <MoeIcenowy> and maybe the adding of hdmi-phy-clk makes exclusive clock necessary

14:56 <jernej> but why would be a change needed? they should all run at the same rate

14:57 <MoeIcenowy> I think it's that the U-Boot currently initializes the clock in another way

14:57 <jernej> so why I observed same issue on R40?

14:59 <MoeIcenowy> but at all we should set the exclusive mode

15:00 <MoeIcenowy> the common clk framewr

15:00 <MoeIcenowy> framework

15:00 <MoeIcenowy> is complex

15:00 <MoeIcenowy> and you shouldn't predict its behavior

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15:10 <MoeIcenowy> jernej: for your resolution changing test could I replace it with monitor switching?

15:10 <MoeIcenowy> (different resolution monitor

15:11 <jernej> It's not the same

15:11 <jernej> I think

15:11 <MoeIcenowy> but I think this will also change dotclock

15:12 <jernej> it will, but not by same procedure

15:12 <jernej> compiling modetest as I pointed in email shouldn't be hard

15:13 <jernej> I don't agree with your statement that I shouldn't predict what clk framework is doing

15:13 <jernej> I spend quiet some time debugging it when developing HDMI drivers

15:14 <jernej> otherwise I wouldn't discover some shortcomings in H6 case

15:15 <MoeIcenowy> any example?

15:16 <MoeIcenowy> jernej: btw here's the operation done to get the 48MHz clock

15:16 <MoeIcenowy> (by sequence)

15:17 <MoeIcenowy> tcon1 <= 32MHz, hdmi <= 32MHz, hdmi_phy_clk <= 32MHz, hdmi_phy_clk <= 32MHz

15:17 <jernej> for example: https://github.com/jernejsk/linux-1/commit/92ff9e0f3b2ae4cfb206a15ed271640eb8a8a648

15:18 <MoeIcenowy> start state and end state are mentioned above

15:18 <jernej> and https://github.com/jernejsk/linux-1/commit/64efaa45c0b56a68dcffea4414b3655e5c5bc419

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15:18 <MoeIcenowy> will you find how is 48MHz out by reviewing this?

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15:19 <jernej> not without poking around live system

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15:19 <jernej> in R40 case, I got 48 MHz clock when I disconnected and reconnected waveshare monitor

15:20 <jernej> it might be the same reason

15:20 <jernej> or not

15:21 <MoeIcenowy> but I think the set of pll-video0 must affected clocks

15:22 <MoeIcenowy> BTW the minimal rate is set in this patchset

15:22 <MoeIcenowy> (for pll-videi0

15:22 <MoeIcenowy> pll-video0 *

15:23 <MoeIcenowy> ok going to sleep, bye

15:24 <jernej> good night

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23:49 <MoeIcenowy> jernej: I think I got why 32MHz become 48MHz

23:49 <MoeIcenowy> it happens during the transtion of pll-video0 from 128MHz to 192MHz

23:49 <MoeIcenowy> 128:32 = 192:48

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