rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<wens> popolon: you should probably be asking arch and over in #linux-rockchip
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<MoeIcenowy> jernej: thx
<MoeIcenowy> popolon: the txt flie is module specific
<MoeIcenowy> e.g. the RPi 3B Wi-Fi module shares the same chip with Ampak AP6212
<MoeIcenowy> but the txt file is different
<MoeIcenowy> jernej: btw where's the maximum patch?
<MoeIcenowy> I only have a minimum patch here
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<wens> MoeIcenowy: really? # ap6212
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<anarsoul> MoeIcenowy: he said he sent similar for H3 and co
<anarsoul> so probably check ML?
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<MoeIcenowy> wens: yes
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<wens> oh, interesting, they put up .txt for ap6212
<MoeIcenowy> yes, just found this today
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<jernej> MoeIcenowy: there is no max. rate patch for A64 yet
<jernej> just add it to min. rate patch
<jernej> other patches are already in linux-next
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<wens> hmm, how is zpos supposed to be interpreted? 0 as top-most or bottom-most plane?
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<MoeIcenowy> jernej: ok I will add it
<MoeIcenowy> what's the rate? 1008000000?
<MoeIcenowy> (according to bsp clk-sun50iw1_tbl.c
<jernej> MoeIcenowy: Good question, datasheet will probably say 600 MHz
<jernej> but in this case I trust BSP code more
<MoeIcenowy> so I will copy your sentence ;-)
<MoeIcenowy> yes user manual says 600MHz
<MoeIcenowy> jernej: why don't you do rebase on your h6_hdmi_v1?
<jernej> what should I rebase?
<MoeIcenowy> the fixup and the added patch
<jernej> I will, before I'll send the patch out
<jernej> *pateches
<jernej> *patches
<jernej> anyway, I plan to work on it a bit
<jernej> like commit messages, adding DT bindings for some compatibles, etc.
<MoeIcenowy> btw why d呕吐
<MoeIcenowy> why do TCON_TOP work
<MoeIcenowy> in U-Boot?
<MoeIcenowy> (wrongly switched IME
<MoeIcenowy> because U-Boot uses full writel but Linux only changes bit mask?
<jernej> yes
<MoeIcenowy> oh maybe this is the key!
<MoeIcenowy> I will try
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<jernej> you also wrongly set TCON fallback compatible
<jernej> A83T doesn't set TCON TOP mux, but R40 does
<MoeIcenowy> A83T?
<MoeIcenowy> oh
<jernej> check fixup commit
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<MoeIcenowy> jernej: to be honest in this situation I prefer to set it to 600, to be conservative
<MoeIcenowy> however, to keep consistency with other SoCs with your patch, I will set it to 1008
<jernej> it's not in DT, so it can be changed later
<jernej> with higher rate we allow more precise rates
<jernej> I mean pixel clock rate
<jernej> anyway, I have to go
<jernej> please just let me know if H6 HDMI works for you or not
<jernej> bye
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<MoeIcenowy> jernej: should we drop PLL-VIDEO1 from A64 HDMI?
<MoeIcenowy> or just keep it there now?
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<anarsoul> MoeIcenowy: drop it if it doesn't work.
<anarsoul> it makes to sense to keep it, if someone figures out how to get it working he can re-add it
<anarsoul> *no sense
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<DonkeyHotei> [Tue 2018-08-28 08:24:07 PM PDT] <MoeIcenowy> popolon: the txt flie is module specific
<DonkeyHotei> [Tue 2018-08-28 08:24:26 PM PDT] <MoeIcenowy> e.g. the RPi 3B Wi-Fi module shares the same chip with Ampak AP6212
<DonkeyHotei> [Tue 2018-08-28 08:24:32 PM PDT] <MoeIcenowy> but the txt file is different
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<popolon> DonkeyHotei: thank you, I just realized that I was on the wrong channel, I thought I was on archlinuxarm
<popolon> archilinu-arm
<popolon> but you answer help me
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<parco> i'm wondering how incorrect panel timings could be locking up the entire display stack?
<parco> i'm seeing a lot of these: [drm:drm_atomic_helper_wait_for_dependencies] *ERROR* [CRTC:40:crtc-0] flip_done timed out
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<parco> doesn't the tcon0 only drive the DSI output, and raises interrupts for vsync internally?
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<bbrezillon> parco: my understanding is that tcon is feeding the DSI FIFO, and the DSI takes data out of this FIFO when sending video frames
<bbrezillon> maybe the TCON just stops feeding the FIFO if there's an overrun (FIFO full)
<bbrezillon> and the VSYNC event never gets generated
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<ptz> not a sunxi-specific question, I would think, but I'll try. So that i don't repeat myself: https://unix.stackexchange.com/questions/465491/ioctl-ttys1-not-a-tty-device
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<ptz> i guess the question is this: i want the uart to be treated as an rs485 by the kernel. is that possible?
<MoeIcenowy> jernej: I have checked that HDMI TMDS clock under PLL-VIDEO1 works
<MoeIcenowy> should we change sun50i-a64-hdmi-phy to sun8i-r40-hdmi-phy and use sun8i-h3-hdmi-phy for A64?
<MoeIcenowy> jernej: I think I need to do more experiments on pll-video1
<MoeIcenowy> with pll-video1 at 192MHz and tcon1 & hdmi & hdmi-phy at 32MHz
<MoeIcenowy> it's able to display something
<MoeIcenowy> although corrupted
<MoeIcenowy> this also happen when only pll-video1 is disabled or hdmi is disabled
<MoeIcenowy> oh I mean only the pll-video1 parent of hdmi disabled or of hdmi-phy is disabled
<MoeIcenowy> but this may be clock freq issue
<MoeIcenowy> I remember you mentioned for it to work hdmi and hdmi-phy must > tcon1?
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<MoeIcenowy> jernej: pll-video1 = 192MHz, hdmi tmds = ~55MHz (under pll-video0) , hdmi-phy = tcon0 (under pll-video1) = 32MHz works
<MoeIcenowy> oh hdmi tmds = tcon0 (under pll-video1) = 32MHz, hdmi-phy (under pll-video0) = ~32.5MHz works
<MoeIcenowy> maybe it's still the HDMI driver's issue
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<MoeIcenowy> for example, the relation should be >, not >=?
<MoeIcenowy> ok let me keep the current DT and wait for more constraints to be found
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<MoeIcenowy> jernej: with your newest now HDMI works well
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<MoeIcenowy> on I mean H6 above
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<micken> MMC adventure goes on. In the a64 manual it states that the dma buffer size for each desc should be a multiple of 4.. Is that like size/4 or just dividable by 4?
<DonkeyHotei> a multiple of 4 generally means divisible by 4
<micken> also when using idma, I have a long wait for the bytecounter to get up to the full transferlength
<micken> DonkeyHotei: I assumed that, thanks
<micken> up to 16k which is my max transfer for each desc, there is no wait , it happens after the 16k limit
<micken> the buffer is actually sized for the whole transfer , and easch desc points to offsets in it
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<jernej> MoeIcenowy: that HDMI limitation (HDMI clk > TCON clk) is for H6
<jernej> but, it may be true for other SoCs as well
<jernej> I believe that DW HDMI 1.32a doesn't really care what is HDMI TMDS clock
<jernej> phy clock rate is more important
<jernej> my theory is that HDMI TMDS and PHY clk both support only PLL_VIDEO0
<jernej> so as long as you keep PLL_VIDEO0 on by some means and on right frequency, it will work
<jernej> I hope TL gets some answer from AW about that
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<webuser5224[m]> I connected a USB webcam to my Orange Pi PC with armbian bionic and a minimal xfce desktop environment (if that information helps any) and tried a few different settings with guvcview via MJPEG and the maximum I get in the preview are around 10-15 FPS at around 240p.
<webuser5224[m]> I'm not sure if this question even fits in here, but since I have no experience of what to expect: Is that an average result?
<webuser5224[m]> I wanted to output 720p at 60 FPS to my screen, so I suppose in my case I can forget about using most SBCs?
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