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<messpl>
Hello guys, have you ever used USB OTG port in host mode?
<messpl>
I have problems with setting it up.
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<ScrumpyJack>
o/
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<hitech95>
Hi guys is there here someone that have experience with the AXP PMIC? I have a couple of questions regarding how to set the default values for the converters and what happend once the power is gone.
<hitech95>
The datasheet says: "The default voltage setting: each channel DCDC / LDO May be selected from a set range including the lowest voltage to the highest voltage.
<hitech95>
about this part, see "Default Configuration instructions" document."
<anarsoul>
looks OK to me, LINEIN is the only orphan, but it's on purpose - it's not connected anywhere on pine64 or pinebook
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<anarsoul>
wens: thanks a lot for the script :)
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<wens>
MBIAS looks out of place
<wens>
the clocks and resets probably need some adjustment, but so does the sun8i one
<wens>
anarsoul: also, the graph should change based on the controls you set
<anarsoul>
wens: MBIAS seems to be OK to me
<anarsoul>
it's internal microphone
<wens>
and if you are playing or capturing, the active paths would change to green
<anarsoul>
wens: OK, will try tonight
<wens>
anarsoul: oh, then you should add a widget for it
<anarsoul>
wens: OK, will do
<wens>
as I see it, the inputs and ouputs of the codec are not the final endpoints; those are the "Jack", "Microphone", "Speaker" widgets
<anarsoul>
that is the graph from pinebook, it has 2 internal mics
<anarsoul>
and external mic jack which is muxed with 2nd internal mic (looks like no sw control - when it's plugged it replaces 2nd internal mic)
<wens>
is there a GPIO to sense that?
<wens>
btw, don't use the "Mic" and "Headset Mic" widgets from sun8i-codec. They shouldn't be there in the first place.
<anarsoul>
nope, jack support should be added to sun50i-codec-analog and sun8i-codec
<anarsoul>
wens: OK
<anarsoul>
wens: I'll implement it later, IIRC it's not straightforward
<hitech95>
wens, You should had told me you had that megic script to see all the dpams. I'm still tring to find out some free time to finish the A33 patch for the digital seconon of the codec. (I went on holiday and than university started and now I also work. Dammit)
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<wens>
anarsoul: jack support?
<wens>
jacks or mics are board level concepts
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<jaganteki>
hi, anyone checked or tried PLL_MIPI on A64 or any other SoC.
<jaganteki>
Manual says the min to max range has 500Mh to 1.4Gh
<jaganteki>
but I got nkm dividers are 1,2,1 which is not working..
<jaganteki>
BPI-M64 bsp is using 180Mhz, when I directly assign it on set_rate on ccu_nkm.c it seems working
<jaganteki>
but no I'm unable to manage this range in ccu_nkm_round_rate
<jaganteki>
is PLL_MIPI specific to attached DSI panel?
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<jernej>
jaganteki: I checked few things about MIPI clocks in BSP over the weekend
<jernej>
first, CLK_BUS_MIPI_DSI and thus it's parent PLL_VIDEO0 are always set to 148.5 MHz
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<jernej>
however, TCON0 and it's parent PLL_MIPI rates are dependant on MIPI display pixel frequency
<jernej>
I assume you have 4 lane MIPI display with 24 bit per pixel and 30 MHz pixel clock, right?
<jernej>
yes, correct
<jaganteki>
yes
<jernej>
so, PLL_MIPI is set to (24 / 4) * 30 MHz = 180 MHz
<jernej>
and TCON0 to 30 MHz
<jernej>
let me check again
<jaganteki>
I can see tcon-pixel-clock is 30MHz on clk_summary
<jaganteki>
why 24 PLL_VIDEO0 is 297Mhz right?
<jernej>
PLL_VIDEO0 might be 148.5 MHz in BSP case
<jernej>
do you have BSP kernel running?
<jernej>
can you check that?
<anarsoul|2>
wens: jack detection is soc-wide at least on A64
<jernej>
Can you also check what are TCON0 clock settings? Rate might be 180 MHz as well
<jaganteki>
I see PLL rate = 180000000, parent = 297000000
<jaganteki>
in get_factors_pll_mipi
<anarsoul|2>
i.e. no extra GPIOs or anything is necessary, it's supported on SoC level
<jernej>
jaganteki: ok, that makes sense, since then CLK_BUS_MIPI_DSI clock is just PLL_VIDEO0 / 2 = 148.5 MHz
<jernej>
can you check TCON0 clock?
<anarsoul|2>
wens: did you notice that codec node has an interrupt? That's used for sensing jack insertion
<jaganteki>
but I'm not sure this (24 / 4) * 30 MHz becuase PLL_MIPI = (PLL_VIDE0 *n *k)/m right?
<jernej>
I'm not talking about PLL_MIPI factors
<anarsoul|2>
wens: and IIRC the problem is that registers to confirm interrupt and check jack status are in different parts of codec, former is in digital part of codec, latter is in analog controls part
<jernej>
I'm talking how MIPI display driver calculates wanted frequency
<jaganteki>
Ok
<anarsoul|2>
wens: so I have no idea at the moment how to implement it properly :\
<jernej>
(1,2,1) are register values (n-1, k-1, m-1) or logical values (n, k, m)?
<jaganteki>
_nkm.n, _nkm.k, _nkm.m
<jaganteki>
values
<jaganteki>
logical values, after this reg |= code for -1 and masking
<jernej>
something doesn't add up
<jernej>
(297 MHz / 1 / 2) / 1 = 148.5 MHz and not 180 MHz
<jaganteki>
I got rate = 390000000 and parent 195000000 in set_rate when I use min 500Mhz and max 1.4 GHz in round rate
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<jaganteki>
(195 * 1 * 2) / 1 = 390
<jernej>
ah, ok
<jernej>
but what is target rate?
<jaganteki>
do you mean the min_rate?
<jaganteki>
w/o having min and max it showing 270Hz
<jernej>
I guess you don't set PLL_MIPI directly, but TCON0 and MIPI DSI clocks
<jernej>
at least you should
<jaganteki>
is the rate return by round_rate
<jernej>
what are PLL_MIPI factors on BSP?
<jaganteki>
1, 2, 5
<jaganteki>
where rate is 180 and parent is 297
<jernej>
can you also check what is TCON0 rate on BSP?
<jaganteki>
sorry BSP nkm are 0, 2, 4
<jernej>
I'm not sure, you can't divide by 0 :)
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<jernej>
Maybe 1, 3, 5? that gives 178.2 MHz
<jaganteki>
that means=> 1, 3, 5
<jaganteki>
I noted reg values
<jaganteki>
(297*1*3)/5= 178.2
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<jernej>
I have to go, I'll come back later
<jaganteki>
I'm checking TCON0
<jaganteki>
I will reply on mail, please have a look
<anarsoul|2>
wens: btw, do you want me to include a patch that drops "Mic" and "Headset Mic" widgets from sun8i-codec.c?
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<curlybracket>
Hello. With PLL_VIDEO0 fixed at 297 MHz (because of MIPI), could there be a way to run the HDMI PHY on A64 at ~204 MHz? So far I could only get it working at 148.5 MHz or 297 MHz. I can force the 204 MHz by tweaking the SUN8I_HDMI_PHY_PLL_CFG1/2 registers, but then the video gets broken. With PLL_VIDEO0 at 204 MHz it runs flawlessly but then I lose the MIPI :/
<anarsoul|2>
curlybracket: I guess using pll_mipi for mipi and pll_video0 for hdmi should ass some flexibility
<anarsoul|2>
but as far as I know no one did it yet
<anarsoul|2>
s/ass/add
<anarsoul|2>
:)
<curlybracket>
I thought pll_mipi needs pll_video0 as a parent, does it not?
<jernej>
it does
<jaganteki>
yes, pll_video0 is parent for pll_mipi
<jaganteki>
jernej, BSP pll_rate shows 180MHz
<jernej>
you mean TCON0?
<jaganteki>
lcd_div is 1
<jernej>
ah, yes
<anarsoul|2>
curlybracket: yeah, unfortunately
<jaganteki>
how can I check TCON0, because PLL_VIDEI0 is 297 which is parent for PLL_MIPI
<jernej>
you can use devmem2 program and read directly from memory
<jernej>
0x01c20118
<jernej>
that way you get divider
<anarsoul|2>
or if driver uses regmap check out /sys/kernel/debug/regmap
<jaganteki>
I have alredy read this values
<jaganteki>
let me check
<jernej>
anarsoul|2: we are talking about BSP :)
<anarsoul|2>
oh, ok :)
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<jaganteki>
0x80000000
<jernej>
which means divider 1
<jaganteki>
devmem 0x01C20118 value
<jernej>
so, TCON0 is also 180 MHz, but you have 30 MHz
<jernej>
I mean BSP kernel TCON0 = 180 MHz and mainline kernel TCON0 = 30 MHz
<jernej>
do you have HDMI monitor enabled alongside MIPI ?
<jernej>
s/enabled/connected/
<jaganteki>
Not enabled HDMI
<jaganteki>
only dsi
<jaganteki>
with mixer0 pipeline enablement
<jernej>
hm... mainline kernel avoids using pll_mipi
<anarsoul|2>
jernej: why?
<jernej>
since it is just intermediate part and nobody is referencing it directly
<jernej>
so clk framework is free to chose another parent
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<jernej>
and currently I didn't see anything in documentation which would mandate usage of PLL_MIPI for MIPI DSI display, despite of it's name
<jaganteki>
then how come A33 is using since it was dsi added before?
<jernej>
However, it might be important, no way to tell without making a lot of tests or asking AW
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<jernej>
A33 has slightly different clocks
<jernej>
if you take a look at TCON0 clock, different parents in different order
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<jernej>
this is enough to have different outcome
<anarsoul|2>
jernej: I'm afraid asking AW may yield no answer :)
<curlybracket>
jaganteki: with the HDMI PHY PLL forced to 204 MHz and pll-video1 also at 204 MHz, I get to see the video for a while (40 seconds maybe). Does the PHY allow correcting the phase of its PLL?
<anarsoul|2>
curlybracket: I think experiments showed that tcon1 can't be clocked from pll-video1
<anarsoul|2>
MoeIcenowy: ^^
<jernej>
anarsoul|2: curlybracket: A64 HDMI PHY can't be clocked from PLL_VIDEO1
<anarsoul|2>
jernej: oh, OK
<jernej>
TCON1 can be
<jaganteki>
yes, ie experinetally true not with manual
<jaganteki>
MoeIcenowy, jernej observed this I think
<anarsoul|2>
that's unfortunate anyway
<jernej>
manual doesn't say anything about HDMI PHY actually, so everything is based on tests
<jaganteki>
jernej, I think it's not possible to configure PLL_MIPI if we enable DSI and HDMI same time is it?
<jernej>
why not? BSP does it
<jernej>
but much more controlled and limited
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<jaganteki>
ok
<jernej>
it will be big PITA on mainline to have them both running at the same time
<jernej>
BSP HDMI derives everything from 297 MHz PLL_VIDEO rate
<jernej>
hm...
<jernej>
One could use PLL_VIDEO0 and PLL_VIDEO1
<jernej>
* and another PLL_VIDEO1
<jaganteki>
this look comeplex configuration because min rate 500MHz on mipi rouned 195Mhz for pll-video0 which might broke HDMI
<anarsoul|2>
jernej: use PLL_VIDEO0 as 297 MHz input for HDMI and PLL_MIPI for the rest?
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<jernej>
anarsoul|2: limiting PLL_VIDEO0 to 297 MHz works only for standard resolutions and some other
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<anarsoul|2>
jernej: but we can use PLL_MIPI as TCON0 input?