<pgreco>
your mail says applied, but I can't find it applied anywhere :D
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<wens>
hmm... did it get accidentally dropped during a rebase?
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<rellla>
mripard, paulk-leonov: it runs fine now. i just have to find out what caused the issue... i'm bisecting now. it was either the PHYS_OFFSET substraction or the missing alignment of the chroma plane which jemk fixed. i can't remember which code my actual kernel is based on :)
<montjoie>
anyone booting sun8i-h3-libretech-all-h3-cc with recent next ?
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<rellla>
mripard, paulk-leonov: seems i fixed the problem. it was neither cedrus nor drm related. it was because of drm_fourcc.h, which has to be synchronized between libdrm-sun4i and the kernel. with 4.19 "#define DRM_FORMAT_MOD_VENDOR_ARM 0x08" was introduced, so this also has to be taken for libdrm-sun4i's drm_fourcc.h
<paulk-leonov>
rellla, oh I see
<paulk-leonov>
so the value we picked for allwinner is now taken by ARM?
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<rellla>
i also can confirm, that i can change the alpha value on the plane with zpos=0 with modetest, so the lowest_alphq quirk can be enabled for a10 - if this is, what is intended with the quirk
<Net147>
Now just need HDMI audio and you can make a media center =D
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<MoeIcenowy>
wens, mripard: I met the dotclock accuracy rounding problem when trying ANX6345 driver
<MoeIcenowy>
as the dotclock check is present to prevent TCON processing with not processable frequency
<MoeIcenowy>
should we change it to a check to a maximum value and a minimum value?
<wens>
see the old 5% tolerance patch ...
<MoeIcenowy>
yes
<MoeIcenowy>
I will send it as a DO NOT MERGE part of my ANX6345 patchset
<MoeIcenowy>
to make people possible to test it
<Net147>
wens: I had issue with the 5% tolerance patch using AT070TN9X. The display had some pixels flickering so I had to manually adjust the pixel clock.
<Net147>
wens: still better than nothing though...
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<Net147>
wens: I used 33 MHz instead of 33.333 MHz to get rid of flicker
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<wens>
Net147: I see
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<adjtm>
pgreco, aren't all allwinner A20 based boards limited at about 450Mb/s ethernet?
<adjtm>
I think that it's an internal bus limitation of that generation of allwinner SOCs
<pgreco>
adjtm, that may be true (and even less wouldn't surprise me)
<pgreco>
but a 90% loss on a ping is not reasonable ;)
<adjtm>
I think that it's indeed if you make simultaneous use of Gbit ethernet and other ports, specially SATA
<adjtm>
90% ping package loses is not normal with Lime2
<KotCzarny>
in the worst you can try vendor kernel to compare
<KotCzarny>
or even legacy one
<adjtm>
I think that it's indeed if you make simultaneous use of Gbit ethernet and other ports, specially SATA (this was about "adjtm, that may be true (and even less wouldn't surprise me)")
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<adjtm>
if ethernet works so bad I would first check other things, like the cable
<ElBarto>
adjtm: bad phy line delays will cause the same problem as a bad cable
<plaes>
yeah ^^
<KotCzarny>
also, wasnt a20 susceptible to some tx timing gotchas?
<ElBarto>
but yeah checking cable is step #1 :)
<ElBarto>
KotCzarny: every gigabit link is susceptible to tx/rx delay problems
<adjtm>
yes, line delays are tricky, but trying with another cable is far easier to check
<pgreco>
agreed, that cable is the first step, but that feels way too similar to montjoie's problem with his bpi-m3
<ElBarto>
KotCzarny: iirc per the standard you need 10cm trace on the pcb with <some width>, that's why the delay registers exists
<ElBarto>
that's between the MAC and the PHY
<ElBarto>
pgreco: same symptoms doesn't mean same problem
<pgreco>
I asked the bug reporter for the board revision
<pgreco>
and I'll start from there
<pgreco>
lime2 changed many things along the way
<pgreco>
including the eth phy twice....
<ElBarto>
yeah
<ElBarto>
I like olimex product because they are reliable but they change so many things each time ..
<ElBarto>
it's a mess
<pgreco>
and you start wondering why did they change that ;)
<KotCzarny>
on the other hand you have orange-like board spewing with new names ;)
<ElBarto>
KotCzarny: at least you can differentiate them by the name !!! :)
<KotCzarny>
but they are basically the same design, with minimal changes
<KotCzarny>
:)
<ElBarto>
(but it's a mess too I agree :P)
<ElBarto>
yeah but minimal change in HW could be huge change in DT
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