<tpb>
Title: RFC: Direct link between Rocket/mem_axi <--> LiteDRAM dataport by gsomlo · Pull Request #300 · enjoy-digital/litex · GitHub (at github.com)
<somlo>
in other words, instead of "mem_axi <-> mem_wb <-> wb_converter <-> litedram_wb <-> litedram_native"
<somlo>
I could do "mem_axi <-> litedram_axi <-> litedram_converter <-> litedram_native"... Maybe this latter one would be more efficient?
<somlo>
it's for the "fallback" case when there's no variant of a cpu with a mem_axi width matching the available litedram default port width
<somlo>
_florent_: I finally get it, line 312 is when port.mode is "both", and we'd obviously need that to work before anything I just said (above) would make sense
<somlo>
sorry, had a long day afk and now trying to find two remaining brain cells to rub together :) :)