<_florent_>
somlo: are you sure it's worth having an AXI ports with data_width > 64-bit on rocket? If you want to do some test with 64-bit AXI with the trellis board, you can also change the platform file and only keep 1 dm, 8 dq, 1 dqs. It will also divide the memory size by 4, but should allow you to evaluate the performance until we have AXI converters.
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<somlo>
I kept R26 for dm, the first row of dq, and R29 for dqs_p
<somlo>
but now nextpnr fails with "terminate called after throwing an instance of 'std::out_of_range'"
<somlo>
"what(): _Map_base::at"
<somlo>
"Aborted (core dumped)"
<somlo>
so I'm probably butchering the platform file in some way that currently escapes me :)
<somlo>
daveshah: yosys git #f02623a, nextpnr git #b582ba8, so not sure they're old enough to qualify for one of the known issues, e.g. https://github.com/YosysHQ/nextpnr/issues/310
<tpb>
Title: nextpnr-ecp5 throws std::out_of_range when using TRELLIS_SLICE · Issue #310 · YosysHQ/nextpnr · GitHub (at github.com)
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<daveshah>
somlo: nothing to do with your change, it's the ECLKBRIDGE change
<tpb>
Title: targets/trellisboard: use ECLKBRIDGECS to allow ECLK to reach all DDR… · litex-hub/litex-boards@5bd8c4d · GitHub (at github.com)
<somlo>
daveshah: thanks!
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<daveshah>
somlo: should be fixed upstream now
<somlo>
oh, cool, I'll just give that a spin, then
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<bonzibuddy>
Hey all - i'm having trouble figuring out where I would increase the allocation for ramdisk in the memory space, on the linux-on-litex-vexriscv project
<bonzibuddy>
i feel like images.json has to line up with some other setting elsewhere?
<bonzibuddy>
ah. soc_cles.mem_map looks promising
<bonzibuddy>
+ json2dts.py
<bonzibuddy>
if there are other spots where 'changing ramdisk size' would come into play id love to hear it :)