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<scanakci> @somlo: how do you try different frequencies when programming Rocket? I have a genesys2 board, and using genesys2.py in Litex to generate the bistream. I noticed that the clock is 300MhZ by default and want to set it to lower.
<scanakci> I changed these two lines to 20MhZ but do not think it worked https://www.irccloud.com/pastebin/0S4h2R7e/
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
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<_florent_> scanakci: you only need to modify sys_clk_freq parameter: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/genesys2.py#L47
<tpb> Title: litex/genesys2.py at master · enjoy-digital/litex · GitHub (at github.com)
<_florent_> this will configure the PLL to generate the specified sys_clk_freq
<somlo> skanakci: what _florent_ said :) I use e.g. "--sys-clk-freq=65e6" to request 65MHZ
<somlo> _florent_: I just figured out that I *could* configure Rocket's mmio_axi port to be 32 bit wide, in which case Rocket will internally handle the data_width conversion
<somlo> the interesting thing about that is that e.g. a 32-bit MMIO access will *not* result in a two-beat burst of 32bits each, with one of the beats strobed out
<somlo> rather, a single beat of 32 bits is issued
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<somlo> this would have been good to know when I was struggling to figure out why adjacent 32bit registers were being clobbered :)
<somlo> however, I think I like the idea of 64bit MMIO registers on 64bit architectures, so I don't plan on taking advantage of this
<somlo> feels like bumpging the csr/mmio LiteX bus width to 64bit when the CPU is a 64bit one should be the goal, instead.
<somlo> any thoughts ?
<_florent_> somlo: yes 64-bit csr/mmio is probably better
<scanakci> thanks!
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<scanakci> (ERROR: [Synth 8-6156] failed synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813]
<scanakci> )
<scanakci> Setting to 25 MHz caused this error. Are there some constraints when setting the frequency?
<scanakci> default is 125MHz and I can generate the bitstream for that frequency
<scanakci> sorry, setting to 20MHZ caused the issue. 25MHz looks working, at least did not get the same error.
<Finde> scanakci: likely this is because the MMCM can only generate clocks with particular ratios to each other
<Finde> that would be my guess
<Finde> may not be your exact issue though
<Finde> but something I've had to deal with in the past when configuring MMCM IP in the Vivado GUI
<somlo> scanakci, Finde: same here, e.g. asking for 65MHz for litex+rocket on ecp5versa gives me an error (don't have it handy to cut'n'paste here, sorry)
<somlo> going with 64MHz works, as does trying for 66
<somlo> so I always wrote it off as "ok, some sort of ratio can't work out properly, wiggle around it a bit, close enough, move on"
<somlo> never actually had a chance to investigate the gory details :)
<scanakci> :) okay makes sense
<scanakci> 25 MHZ worked, so I am good for now
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