17:27 <scanakci> @somlo: how do you try different frequencies when programming Rocket? I have a genesys2 board, and using genesys2.py in Litex to generate the bistream. I noticed that the clock is 300MhZ by default and want to set it to lower.

17:28 <scanakci> I changed these two lines to 20MhZ but do not think it worked https://www.irccloud.com/pastebin/0S4h2R7e/

17:28 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

17:29 <scanakci> https://www.irccloud.com/pastebin/YodpQ8ZO/I%20checked%20the%20top.xdc.%20It%20generates%20clk%20with%20period%205ns%20even%20after%20I%20modify%20the%20file.

17:29 <tpb> Title: Snippet | IRCCloud (at www.irccloud.com)

18:28 <_florent_> scanakci: you only need to modify sys_clk_freq parameter: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/genesys2.py#L47

18:28 <tpb> Title: litex/genesys2.py at master · enjoy-digital/litex · GitHub (at github.com)

18:28 <_florent_> this will configure the PLL to generate the specified sys_clk_freq

18:29 <somlo> skanakci: what _florent_ said :) I use e.g. "--sys-clk-freq=65e6" to request 65MHZ

18:31 <somlo> _florent_: I just figured out that I *could* configure Rocket's mmio_axi port to be 32 bit wide, in which case Rocket will internally handle the data_width conversion

18:32 <somlo> the interesting thing about that is that e.g. a 32-bit MMIO access will *not* result in a two-beat burst of 32bits each, with one of the beats strobed out

18:33 <somlo> rather, a single beat of 32 bits is issued

18:33 <somlo> this would have been good to know when I was struggling to figure out why adjacent 32bit registers were being clobbered :)

18:34 <somlo> however, I think I like the idea of 64bit MMIO registers on 64bit architectures, so I don't plan on taking advantage of this

18:35 <somlo> feels like bumpging the csr/mmio LiteX bus width to 64bit when the CPU is a 64bit one should be the goal, instead.

18:35 <somlo> any thoughts ?

19:02 <_florent_> somlo: yes 64-bit csr/mmio is probably better

19:13 <scanakci> thanks!

21:05 <scanakci> (ERROR: [Synth 8-6156] failed synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:39813]

21:05 <scanakci> )

21:06 <scanakci> Setting to 25 MHz caused this error. Are there some constraints when setting the frequency?

21:07 <scanakci> default is 125MHz and I can generate the bitstream for that frequency

21:10 <scanakci> sorry, setting to 20MHZ caused the issue. 25MHz looks working, at least did not get the same error.

21:15 <Finde> scanakci: likely this is because the MMCM can only generate clocks with particular ratios to each other

21:15 <Finde> that would be my guess

21:15 <Finde> may not be your exact issue though

21:15 <Finde> but something I've had to deal with in the past when configuring MMCM IP in the Vivado GUI

21:16 <somlo> scanakci, Finde: same here, e.g. asking for 65MHz for litex+rocket on ecp5versa gives me an error (don't have it handy to cut'n'paste here, sorry)

21:16 <somlo> going with 64MHz works, as does trying for 66

21:17 <somlo> so I always wrote it off as "ok, some sort of ratio can't work out properly, wiggle around it a bit, close enough, move on"

21:17 <somlo> never actually had a chance to investigate the gory details :)

21:29 <scanakci> :) okay makes sense

21:29 <scanakci> 25 MHZ worked, so I am good for now