10:07 <futarisIRCcloud> https://antmicro.com/blog/2019/12/tflite-in-zephyr-on-litex-vexriscv/

10:07 <tpb> Title: Antmicro · Tensorflow Lite in Zephyr on LiteX/VexRiscv (at antmicro.com)

10:24 <futarisIRCcloud> Maybe I should order a PmodACL to play with the above on Arty A7 35T

20:57 <scanakci> I have a question related to running Litex BIOS on FPGA. I generated the bitstream for genesys and programmed the FPGA using JTAG. Now, I would like to see Litex BIOS console after reset. For loading linux images through serial, I see that vexriscv-litex repo uses litex_term. Is this the correct tool to run BIOS only?

20:58 <scanakci> I believe that this one (in Litex README) could a bit more detailed to help beginners like me :) :

20:58 <scanakci> "6. Run a terminal program on the board's serial port at 115200 8-N-1. You should get the BIOS prompt."

21:01 <scanakci> I am trying to see the BIOS console for Rocket as first using this command: ./litex_term.py /dev/ttyUSB0

21:01 <scanakci> After pressing reset, it prints sth that I include in plic_init function but not going further.

21:05 <CarlFK> USB0 .. I don't think that is right

21:12 <scanakci> why do you think so? I checked the dmesg output and looks like ttyUSB0.

21:17 <scanakci> actually now I see that dmesg prints something different than yesterday. thanks @CarlFK for pointing this.

21:25 <scanakci> It is good, I unplugged and plugged back and verified based on dmesg

21:26 <CarlFK> I would expect /dev/ttyACM0 - but that's based on a few other similar things, like fomu

21:26 <daveshah> FTDI stuff like the Genesys is USB not ACM

21:26 <daveshah> It's been a while since I used the Genesys but it may well not be ttyUSB0

21:26 <scanakci> yeah, I was working with zedboard which was using ttyACM

21:26 <daveshah> are there any other ttyUSBs?

21:27 <scanakci> nope, only one

21:28 <scanakci> ttyUSB0 appears after I connect genesys to my desktop and dmesg tells me that "[3521277.129916] usb 1-10: FTDI USB Serial Device converter now attached to ttyUSB0"

21:30 <daveshah> Yeah, definitely the right device then

21:31 <daveshah> Sounds like all the PC side stuff is fine and it is a BIOS or gateware issue

21:34 <scanakci> I see. as a side note, I used "./genesys2.py --cpu-type rocket --cpu-variant standard" to generate the bitstream. @somlo, do I need to add anything to this command line? I only want to see terminal and want to type help. ethernet, LITEDram support are not necessary.

21:34 <daveshah> That sounds fine

21:35 <scanakci> thank you @daveshah.

21:41 <somlo> scanakci: if it works for you that way, you're OK. I for one have to add "--gatware-toolchain-path ...path-to-vivado..." to the command line (I'm assuming you're currently using a xilinx fpga)

21:42 <somlo> but that's only because my Vivado install is in a place other than what LiteX assumes by default :)

21:42 <scanakci> okay, that part is good. vivado looks fine :)