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<acathla> If I want to make a testbench for litex/soc/cores/uart.py, how do I do that? Since it's made to work on a wishbone bus
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<davidc__> acathla: Use bus.write / bus.read to simulate wishbone bus cycles?
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<acathla> davidc__, okay, thank you
<acathla> Is there an example somewhere?
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<davidc__> acathla: I think there are examples in litex itself
<davidc__> (just grep it for "\.write"
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