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<somlo> _florent_: I still don't know where CSR endianness "happens", but while digging around, I stumbled upon csr_bus/SRAM, which should be selected and aligned the same way as CSRBank :) -- https://github.com/enjoy-digital/litex/pull/332
<tpb> Title: interconnect/csr_bus/SRAM: allow 64-bit alignment (on 64-bit CPUs) by gsomlo · Pull Request #332 · enjoy-digital/litex · GitHub (at github.com)
<somlo> _florent_: now, in the future, we might want to consider encoding strings at memory width that's equal to csr_data_width instead of hardcoded-8 (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/identifier.py#L15)
<tpb> Title: litex/identifier.py at master · enjoy-digital/litex · GitHub (at github.com)
<somlo> but that's independent from the current PR
<somlo> oh, and Happy New Year! :)
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