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<xobs> _florent_: thanks, the new UART changes work well! Tunneling via wishbone works, so now `wishbone-tool` can act as a terminal emulator via any of the bridges.
<xobs> It's also growing basic Etherbone support now. So we can have terminal-over-Ethernet.
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<_florent_> xobs: thanks, that will be very useful! I was always switching between the Wishbone Bridge and the CPU UART manually or using 2 UARTs to have both together
<xobs> I also added the ability to run multiple servers at once, so terminal and gdb will both work. Though now I need to add the ability to run gdb on a different port.
<_florent_> xobs: great. Do you have a board to test the terminal-over-Ethernet? I'm happy to do some testing if needed
<xobs> mithro was working to get that built. There were Reasons that it doesn't work. Could you please help him get an image working?
<mithro> I'm looking at it now
<_florent_> mithro: which board are you using?
<mithro> _florent_: I'm stuck at getting the wishbone bridge over ethernet working
<mithro> _florent_: Arty
<_florent_> mithro: are you able to ping the board?
<futarisIRCcloud> This stuff sounds great.
<mithro> _florent_: Let me push what I have so far
<_florent_> mithro: ok
<mithro> _florent_: Also, would like your thoughts on https://github.com/enjoy-digital/litex/issues/345
<tpb> Title: Support register_mem autoselecting appropriate memory location · Issue #345 · enjoy-digital/litex · GitHub (at github.com)
<tpb> Title: litex-buildenv/etherbone.py at etherbone · mithro/litex-buildenv · GitHub (at github.com)
<mithro> _florent_: It took me a while to realize that I have actually mostly done etherbone through libuip rather than with hardware
<_florent_> xobs, mithro: it should be possible to easily test Etherbone with litex_sim: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py
<mithro> _florent_: I did get the ice40hx-evn board actually booting again
<tpb> Title: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)
<tpb> Title: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)
<mithro> _florent_: That is a probably a good idea for xobs to test with :-)
<_florent_> set with_uart=True here and set uart_name="crossover"
<mithro> _florent_: At the moment I'm trying to get that `arty/etherbone.py`to respond to pings on hardware
<tpb> Title: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)
<_florent_> and then just run: litex_sim --with-etherbone
<_florent_> then try to ping 192.168.1.50
<_florent_> if its responding, the Etherbone bridge is responding and you can use it
<_florent_> Etherbone bridge is responding/Etherbone bridge is active
<_florent_> mithro: being able to use add_mem_region without the origin seems a good idea yes. When doing it we should just make sure to avoid breaking the old API and still allow using a fixed memory map
<mithro> _florent_: I believe my python code does that
<mithro> _florent_: Preserves the old method and allows the new method...
<_florent_> mithro: yes probably, i haven't look closely yet :) will do!
<mithro> _florent_: Should have thought about telling xobs to use the sim target...
<_florent_> scanakci: using a frequency that is too low can indeed cause issues for the DDR3 calibration. We have some limitation with the IDELAYE2/ODELAYE2 taps for write/read leveling
<mithro> _florent_: After building that etherbone example I linked above, Ethernet seems to come up but I don't get any arp response or response to ping
<mithro> _florent_: Can the libuip interfere with the hardware etherbone?
<_florent_> scanakci: i would recommend using the max sys_clk_freq you can that don't produce timing violations, the Kintex7 is quite capable so should be able to run your CPU at a higher frequency
<tpb> Title: litex-buildenv/etherbone.py at 4f7b1b37531fe5f0773cf737b4e1b57d6d775165 · mithro/litex-buildenv · GitHub (at github.com)
<_florent_> mithro: for now, you can't connect LiteEthPHY to LiteEthMAC and LiteEthUDPIPCore, you have to choose
<mithro> _florent_: I need to give LiteEthUDPIPCore a LiteEthPHY right?
<_florent_> yes or remove the LiteEthMAC
<_florent_> mithro: here is an Etherbone example: https://github.com/enjoy-digital/usb3_pipe/blob/master/kc705.py#L95-L120
<tpb> Title: usb3_pipe/kc705.py at master · enjoy-digital/usb3_pipe · GitHub (at github.com)
<mithro> _florent_: We should probably have an arty example of etherbone somewhere that is easy to find
<_florent_> mithro: yes i also realized that
<mithro> Doah! I configured IP address of 192.168.1.50 and have been trying to ping 192.168.100.50 ...
<_florent_> is it working now?
<mithro> _florent_: Still no luck :-/
<tpb> Title: litex-buildenv/etherbone.py at 3d2e45db21254fe40e6797262da7bf713ac4e561 · mithro/litex-buildenv · GitHub (at github.com)
<mithro> _florent_: The link is up, but I'm not seeing any arp responses
<_florent_> mithro: ok i need to have a closer look. I tested if on others targets recently but not on Arty
<xobs> Is there any documentation on how to use litex_sim? I'm having to patch Makefiles to add `-I/opt/miniconda3/include` and `-L/opt/miniconda3/lib`, and I feel that's the wrong way to do it.
<_florent_> xobs: litex_sim is simular to others designs, just that it uses Verilator as a backend for the simulation
<_florent_> xobs: so you just need to install Verilator + libevent-dev libjson-c-dev (on Ubuntu)
<xobs> _florent_: I see. I had to patch a bunch of files to add the miniconda3 include and library files, and now it's asking me for my password.
<xobs> Does this use tun/tap, then?
<tpb> Title: GitHub - enjoy-digital/litex: Build your hardware, easily! (at github.com)
<_florent_> when adding ethernet, it request the password yes to create the ethernet tap
<xobs> I see. Then this won't work under WSL :(
<_florent_> but for a first test, you can just execute litex_sim
<xobs> With my patches, I get a teminal. Yay!
<xobs> But TUN isn't implemented under WSL :(
<_florent_> xobs: in fact we are using https://github.com/enjoy-digital/tapcfg
<tpb> Title: GitHub - enjoy-digital/tapcfg: tapcfg (at github.com)
<_florent_> xobs: so it should work with WSL
<_florent_> but not sure i tested
<xobs> `Error opening device /dev/net/tun: No such file or directory`
<_florent_> too bad, litex_sim would have been very useful for adding ethernet support to wishbone-tool
<_florent_> xobs: What's your prefered board to test Etherbone? NeTV2? i could prepare a design for it if you want
<xobs> I'm at LCA, and Tim has an Arty here that's easiest to test with.
<mithro> _florent_: I'm probably doing something stupid with this arty config
<mithro> I managed to just get one reply then...
<mithro> 18:46:28.510005 ARP, Reply 192.168.1.50 is-at 10:e2:d5:00:00:00 (oui Unknown), length 46
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