<xobs>
_florent_: thanks, the new UART changes work well! Tunneling via wishbone works, so now `wishbone-tool` can act as a terminal emulator via any of the bridges.
<xobs>
It's also growing basic Etherbone support now. So we can have terminal-over-Ethernet.
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<_florent_>
xobs: thanks, that will be very useful! I was always switching between the Wishbone Bridge and the CPU UART manually or using 2 UARTs to have both together
<xobs>
I also added the ability to run multiple servers at once, so terminal and gdb will both work. Though now I need to add the ability to run gdb on a different port.
<_florent_>
xobs: great. Do you have a board to test the terminal-over-Ethernet? I'm happy to do some testing if needed
<xobs>
mithro was working to get that built. There were Reasons that it doesn't work. Could you please help him get an image working?
<mithro>
I'm looking at it now
<_florent_>
mithro: which board are you using?
<mithro>
_florent_: I'm stuck at getting the wishbone bridge over ethernet working
<mithro>
_florent_: Arty
<_florent_>
mithro: are you able to ping the board?
<futarisIRCcloud>
This stuff sounds great.
<mithro>
_florent_: Let me push what I have so far
<_florent_>
and then just run: litex_sim --with-etherbone
<_florent_>
then try to ping 192.168.1.50
<_florent_>
if its responding, the Etherbone bridge is responding and you can use it
<_florent_>
Etherbone bridge is responding/Etherbone bridge is active
<_florent_>
mithro: being able to use add_mem_region without the origin seems a good idea yes. When doing it we should just make sure to avoid breaking the old API and still allow using a fixed memory map
<mithro>
_florent_: I believe my python code does that
<mithro>
_florent_: Preserves the old method and allows the new method...
<_florent_>
mithro: yes probably, i haven't look closely yet :) will do!
<mithro>
_florent_: Should have thought about telling xobs to use the sim target...
<_florent_>
scanakci: using a frequency that is too low can indeed cause issues for the DDR3 calibration. We have some limitation with the IDELAYE2/ODELAYE2 taps for write/read leveling
<mithro>
_florent_: After building that etherbone example I linked above, Ethernet seems to come up but I don't get any arp response or response to ping
<mithro>
_florent_: Can the libuip interfere with the hardware etherbone?
<_florent_>
scanakci: i would recommend using the max sys_clk_freq you can that don't produce timing violations, the Kintex7 is quite capable so should be able to run your CPU at a higher frequency
<mithro>
_florent_: The link is up, but I'm not seeing any arp responses
<_florent_>
mithro: ok i need to have a closer look. I tested if on others targets recently but not on Arty
<xobs>
Is there any documentation on how to use litex_sim? I'm having to patch Makefiles to add `-I/opt/miniconda3/include` and `-L/opt/miniconda3/lib`, and I feel that's the wrong way to do it.
<_florent_>
xobs: litex_sim is simular to others designs, just that it uses Verilator as a backend for the simulation
<_florent_>
xobs: so you just need to install Verilator + libevent-dev libjson-c-dev (on Ubuntu)
<xobs>
_florent_: I see. I had to patch a bunch of files to add the miniconda3 include and library files, and now it's asking me for my password.