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<sajattack> yo
<_florent_> sajattack: hi
<sajattack> so how do I get to the bios prompt?
<_florent_> when you load your bitstream, you should get the bios prompt
<sajattack> it's hard to tell because I don't have an ftdi cable, I've got an arduino hooked up reading the uart
<sajattack> it only seems to echo my characters
<_florent_> in the pull request, you are saying that you have echo, but you should also have the LiteX bios prompt
<sajattack> ok I'll try to check
<_florent_> if you send enter, to you get back "litex>"
<sajattack> is enter the same as \n
<_florent_> yes, try both \n and \r
<sajattack> ok
<sajattack> just a minute
<sajattack> doesn't look like it
<sajattack> I only loaded gateware, not software
<sajattack> or firmware or w/e
<sajattack> I'm not getting an echo anymore either
<sajattack> maybe I'll go back a few commits
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<sajattack> ok got it
<sajattack> wiring pebkac
<sajattack> b'hello\n\rCommand not found\n\r\x1b[92;1mlitex\x1b[0m> '
<daveshah> Looks like your terminal isn't a VT100 :)
<sajattack> it's picocom
<sajattack> plus circuitpython
<sajattack> jank hax because no ftdi cable
<sajattack> if it works it works, right?
<sajattack> let me squash and stuff
<sajattack> should be good
<sajattack> can you guys help me get to linux-on-litex next?
<_florent_> sajattack: the bios seems indeed to be working, but you setup does not seem that convenient to use :)
<sajattack> indeed
<sajattack> I at least converted the bytes to ascii now
<sajattack> so it's a little better
<sajattack> maybe I can make it a bit more interactive too
<_florent_> to use linux-on-litex-vexrisc, you need a 32MB memory and on the de10 nano, the DDR3 seems connected to the HPS, so not sure that's easy to access to it from the fabric
<_florent_> the de10 nano is the board used by Mister, and there are SDRAM extension available that you could use: https://github.com/MiSTer-devel/Main_MiSTer/wiki/SDRAM-Board
<tpb> Title: SDRAM Board · MiSTer-devel/Main_MiSTer Wiki · GitHub (at github.com)
<sajattack> yeah I have one of those
<sajattack> but I didn't think it was right to stick an optional addon board in the board def
<_florent_> you could do it the way we did it on the ECP5 Versa when we were using the SDRAM extension: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/official/platforms/versa_ecp5.py#L147-L165
<tpb> Title: litex-boards/versa_ecp5.py at master · litex-hub/litex-boards · GitHub (at github.com)
<sajattack> just reuse the pins?
<_florent_> yes, you could probably find that in the MiSTer project
<sajattack> ok will do
<_florent_> then you will need to see if the SDRAM module is already defined in LiteDRAM: https://github.com/enjoy-digital/litedram/blob/master/litedram/modules.py#L126-L221
<tpb> Title: litedram/modules.py at master · enjoy-digital/litedram · GitHub (at github.com)
<_florent_> if not, we could add it
<sajattack> kk, just doing some circuitpython coding for the last few minutes to have more of an interactive prompt
<sajattack> much better https://termbin.com/z3mo
<_florent_> for the target with the SDRAM integrated, you could look at the de0nano.py: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/official/targets/de0nano.py
<tpb> Title: litex-boards/de0nano.py at master · litex-hub/litex-boards · GitHub (at github.com)
<sajattack> the sdram chips on mister are usually alliance or winbond
<sajattack> I have winbond
<sajattack> but they're compatible with eachother I think
<_florent_> yes probably, but what's the part number?
<sajattack> let me check
<sajattack> Alliance Memory
<sajattack> AS4C16M16SA-6TCN or Winbond W9825G6KH-6
<sajattack> for 32mb
<sajattack> they have 128mb boards too
<tpb> Title: litedram/modules.py at master · enjoy-digital/litedram · GitHub (at github.com)
<sajattack> yay
<sajattack> oh shit I think I typed this in backwards because quartus
<sajattack> so how does this work if they don't have the sdram module?
<sajattack> I'm looking at versa_ecp5 and you're using SoCSDRAM
<sajattack> _florent_: ^
<sajattack> I guess I add a flag like you do with ethernet
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<sajattack> anyone there?
<acathla> hi sajattack
<sajattack> if I push some weird WIP code can you take a look at it and tell me how to do it properly?
<sajattack> I'm getting this error and also I'm committing some python/migen crimes migen.fhdl.module.FinalizeError: CPU needs "rom" to be defined as memory or linker region
<acathla> sajattack, you probably need to define a rom region in your new flash definition
<sajattack> what flash definition?
<acathla> ah, you were talking only about sdram, I didn't backlog enough
<acathla> anyway, your SoC need to have a rom region where you put your bios/bootloader/code to boot to, even if it's in SDRAM.
<acathla> I guess, i'm learning too...
<sajattack> where do I define that?
<sajattack> I checked existing boards platform and target files and didn't see anything with "rom" other than "from" in imports
<sajattack> maybe I'll just try running linux-with-litex as the builder now
<sajattack> that doesn't work for another reason
<acathla> I'm only using small FPGAs yet, without big SDRAM so it's a bit different. Here is the example I'm using : https://github.com/kekiefer/tinyfpga-litex/blob/master/tinyfpga_litex.py
<tpb> Title: tinyfpga-litex/tinyfpga_litex.py at master · kekiefer/tinyfpga-litex · GitHub (at github.com)
<sajattack> it looks like that's a step up from where I'm working
<sajattack> I'm working on a board def
<acathla> But the concept is sadly to read the source with very few comments in it and to try to understnd how it works, until the docs grow...
<sajattack> yeah
<sajattack> oh I think I figured it out
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<sajattack> new problem lol
<sajattack> NameError: name 'fmt' is not defined
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<_florent_> sajattack: sorry i was away, i can have a look if you share your current platform/target files
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<somlo> xobs: https://pastebin.com/DA1KWiyk (on top of the current "common.h")
<tpb> Title: [Diff] diff --git a/litex/soc/software/include/hw/common.h b/litex/soc/software/include - Pastebin.com (at pastebin.com)
<somlo> xobs: then, restore generated/csr.h to use csr_readl() and csr_writel() with shifts
<somlo> would that work for you?
<xobs> somlo: I think it would, yes. Thank you!
<somlo> cool, i'll cook something up for export.py to do that, then...
<somlo> xobs: just saw your last reply on github, so question re. naming convention: stick with readl/writel (as in, "long")? Or rather go with csr_read_sub[reg]() and csr_write_sub[reg]() instead? These are after all subregister accessors, not full-CSR ones... :)
<xobs> Sure, you can do csr_x_sub().
<xobs> I just followed the Linux convention. I tend to think of CSRs as being 8-bit registers with contents spread across multiple fields, but I'm not sure anyone else does that.
<xobs> Comes from working with odd-sized peripherals. Like the i.MX6, which had an 8-bit PWM IP core taken straight from a Coldfire.
<xobs> So `csr_readl()` and `csr_writel()` made sense to me. But I definitely see the confusion, so for this particular instance `csr_x_sub()` could work nicely!
<somlo> I'm used to MMIO registers of 32 and 64 bits, so my instinct is to encapsulate the scatter/gather "striping" of the underlying 8-bit limitation as much as possible :)
<somlo> particularly since LiteX now supports 32bit subregisters, and might support 64bits with a bit more cleanup...
<somlo> ok, so csr_x_sub() it is, then -- thanks for your patience :)
<xobs> I think I'll be moving to 32-bit CSRs, because it makes the software simpler and doesn't impact performance too much. It makes no difference with Fomu, and seems fine with Betrusted, too.
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<tpb> Title: software, integration/export: (re-)expose CSR subregister accessors by gsomlo · Pull Request #366 · enjoy-digital/litex · GitHub (at github.com)
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<sajattack> _florent_: shared
<sajattack> the TODOs and the fmt error are what I'm struggling with
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<futarisIRCcloud> CCC = Chisel Community Conference ?
<sajattack> how do I load a risc-v program to SoCCore?
<sajattack> sfl?
<tpb> Title: litex/litex_term.py at master · enjoy-digital/litex · GitHub (at github.com)
<sajattack> I really need proper ftdi lol
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