<_florent_>
mithro: i'm following a bit the nmigen-soc work yes, things could indeed be probably be improved a lot but it's not possible to have such radical changes for the projects i maintain that are using Migen/LiteX. So i'm also trying to improve LiteX progressively while trying to keep old code compatible or easy to port. One of the next things i want to do is to be able to switch between Migen and nMigen (in compat mode)
<_florent_>
for the verilog generation and then evaluate nMigen while doing a new core. And then see if LiteX should also switch to real nMigen (non compat).
<Claude>
hmm anyone got a hint for me where to look? i have my own ecp5 board with ddr3 mem. i'm using litesdram with a MT41J128M16JT ddr chip which is in the list of drams supported by litedram. the ddr seems to work, the vecx bios memory test doesn't show any errors and i can write and read data in the bios without errors. so far so fine :) but as soon as i use litesdram my fpga and ddr3 chips get quite hot. same board with just
<Claude>
an risc-v blinking around is cool. i think i got the basic ddr3 layout right, because it seems to work. now i supect something in the ODT termination / and or fpga side termination is off. i can almost adjust the temperature of the ddr3 and fpga by changing the fpga side termination value from 50 to 70 to 100 ohms . 50 = hotest , 100 lowest temperature
<daveshah>
A degree of heat is pretty normal tbh
<daveshah>
given those low termination values, the current involved in DDR3 is pretty high
<Claude>
ok so , for example the ecp5 versa ddr3 gets hot too ? with hot i mean almost too hot to touch
<daveshah>
maybe not quite that hot, but certainly a lot warmer than idle
<Claude>
i will take the board on friday at work, then i can look for excessive under/overshot on the ddr3 lines. currently i have build 3 boards and all show the same symptoms
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<Claude>
actually on a cyclone 5 based design with ddr3 all stays very cool. fpga and ddr get lukewarm
<sajattack>
linux soc in 2727 ALMs, love it! smaller than MiSTer framework :)
<sajattack>
4180 luts
<atommann>
_florent_, that's cool. netboot works for KC705, and it's fast.
<_florent_>
atommann: it's indeed a bit faster than serialboot :)
<_florent_>
atommann: how fast is the Linux boot on the KC705? 5-6s?
<atommann>
about 10 seconds.
<_florent_>
including the netboot?
<atommann>
yes.
<atommann>
Last year one of my friend designed a board which uses Xilinx 7K325T.
<sajattack>
hmm, that doesn't look impossible, but this is my first migen project
<atommann>
_florent_, I just called him, compilation passed, I guess he is getting there.
<_florent_>
sajattack: that could be a bit tricky as a first project, but S7HDMIOutClocking generates the pixel clock (with dynamic configuration, but dynamic configuration could be avoided as a first step), and S7HDMIOutEncoderSerializer is doing the 10:1 serialization.
<_florent_>
i'm not well aware of the Altera primitives, if 10:1 is possible or not
<sajattack>
yeah idk
<_florent_>
if not, you will need to use Gearbox to do 10:N and then use the primitive to do N:1, but that becomes a bit complicated for a first project
<_florent_>
sajattack: using VGA with an external extension board would be easier
<sajattack>
yeah
<sajattack>
oh ok
<sajattack>
yeah I have the vga board
<_florent_>
ok, then adding VGA support to Linux-on-LiteX-Vexriscv could be a good contribution and should not be too complicated :)
<sajattack>
yeah I'm fairly familiar with vga in verilog
<sajattack>
my first project was a vga test pattern from 8bitworkshop and I've done some MiSTer stuff too
<_florent_>
ok nice
<sajattack>
MiSTer automagically does vga to hdmi haha
<mithro>
Claude: _florent_ is doing a lot of work around LiteDRAM at the moment -- I'm sure he would be very interested in information like that
<_florent_>
Claude: indeed, that's interesting to know. I'm not sure it was that hot on the ECP5 boards i tested, but i could do more tests if needed. Feel free to open an issue on LiteDRAM to discuss that.
<sajattack>
ok I'll try that soon _florent_
<sajattack>
I'll borrow or buy an ftdi tomorrow
<Claude>
mithro: ok as soon as I'm sure my hardware is okay I will give more feedback
<Claude>
Ok , but first I triple check the hardware:)
<daveshah>
I remember when I was using the TrellisBoard with a weak USB cable, it actually browned out just when Linux started booting. I do suspect increased DDR3 activity was more significant here than anything going on inside the FPGA
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<daveshah>
TrellisBoard just idling is getting warm but not hot, that's the biggest package so might be spreading the heat more. I definitely remember the Versa ECP5 chip getting significantly warmer
<Claude>
Thanks a lot for testing
<mithro>
kgugala: <tumbleweed> mithro: ERROR: [Place 30-640] Place Check : This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 132 of such cell types but only 100 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a
<mithro>
larger device.
<mithro>
kgugala - tumbleweed is trying to work on getting NeTV2 for PCIe going
<mithro>
But I'm unsure how to check given the part is covered by a head sink...
<mithro>
_florent_: Can you use jtag to read which part?
<_florent_>
mithro: as just discussed with kgugala, i just added optional CSRs to LiteDRAM DMAs, this make it very easy to let the CPU program the DMA and from the user logic, just used the source or sink
<somlo>
_florent_: haven't been following the conversation carefully, but +1 to DMA support in LiteDRAM :)
<_florent_>
somlo: the DMA was already there, but the used was generating the address stream, not this can be controlled by the CPU
<_florent_>
so for a DMA Reader, the CPU just programs the base address, length, and start the transfer. The source if the DMA will generate the data and the user can just use it.
<_florent_>
same for a DMA Writer but in the others direction: the CPU programs the transfer and the user provides the data in the DMA sink.
<_florent_>
others/other
<somlo>
I'll have to sit down and study all the moving parts, but I'd love to have DMA support in the LiteX+Rocket computer (I think LiteETH would/could be much faster that way)
<_florent_>
somlo: in fact there were already similar features in LiteVideo, but directly integrated in LiteVideo. Here it becomes more generic and usable for others purposes. (for example here we want to use the DMA Reader to read data from the DDR3 and send it to the PCIe DMA and the opposite).
<tpb>
Title: WIP: Attempt at doing a better add_memory_region by mithro · Pull Request #369 · enjoy-digital/litex · GitHub (at github.com)
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<andresfcalderon>
Hi, I'm new here ... but I've already begun to see the magic of LiteX
<andresfcalderon>
Currently I'm testing LiteX on an unsupported board (MATRIX Voice), the board has an FPGA XC6SLX9 with 64MBytes of DDR2. The initialization seems fine (Memtest OK) https://imagebin.ca/v/5AeUVHjSE9dD
<andresfcalderon>
I got an error booting:
<andresfcalderon>
[FLTERM] Got unknown reply 'T' from the device, aborting.
<andresfcalderon>
the full boot message:
<andresfcalderon>
--============== Boot ==================--Booting from serial...Press Q or ESC to abort boot completely.sL5DdSMmkekro[FLTERM] Received firmware download request from the device.[FLTERM] Uploading kernel (50356 bytes)...[FLTERM] Got unknown reply 'T' from the device, aborting.[FLTERM] Booting the device.[FLTERM] Got unknown reply 'i' from the
<andresfcalderon>
device, aborting.meoutBooting from flash...Error: Invalid image length 0xffffffffNo boot medium found
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<mithro>
xobs: I don't think the loopback uart is working for me anymore...