<mithro>
Out of order RISC-V core targeted at an FPGA done by a group of japanese researchers!
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<scanakci>
_florent_: I am testing Blackparrot on FPGA with LiteDRAM. Although memory tests are successful in simulation, they fail on an FPGA. I noticed that the problem is most probably related to clock frequency. If I generate a bitstream for genesys using rocket and vexriscv with default frequency (125MHz), memory tests pass. When I set clock to 25MHz, they fail. My guess is that Blackparrot fails for the similar reasons.
<scanakci>
Bitstream is generated succesfully, run BIOS but memory tests with LiteDRAM fails. Did you test these two cores on genesys with different frequencies before?
<daveshah>
I've definitely seen issues with litedram at reduced frequencies before. Both on ECP5 (but only some TrellisBoards for some strange reason, no Versas that I know of), and I think a Xilinx board too
<daveshah>
60MHz+ is usually fine
<scanakci>
thanks @daveshah. I hope current version of blackparrot works fine around that frequency.
<somlo>
scanakci: with rocket, I usually get 75MHz on nexys4ddr with vivado, and 45-55 "official" MHz on versa and trellis with yosys/trellis/nextpnr. it "fails" to pass the 60MHz I'm asking of it, but usually works fine (per daveshah, there's a fair amount of extra slack in the tooling)
<somlo>
I only say that because, if Blackparrot is simpler/smaller than Rocket, you *should* be able to get 60MHz out of it :)
<somlo>
s/in the tooling/in the silicon, that the tooling isn't aware of/
<daveshah>
And the k7 in the Genesys2 should be faster than both the nexys4 and the versa
<scanakci>
thank you @somlo. I think I will play with frequency and try to fine-tune it
<scanakci>
@daveshah, true. Its specs look better than nexys4ddr and trellis.
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<Finde>
scanakci: Fei just tried the memory write/read to 0x40000000 and saw success so it looks like you were right about the address being the problem :)
<scanakci>
Finde: good to hear that :)
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