00:27 <Finde> given that, if you want a standalone litedram, using vexriscv internally to calibrate, then do you end up with a DRAM with like a 64b width?

01:11 <somlo> Finde: I'll let _florent_ answer that authoritatively, but there's no reason why the externally accessible port exposed by a "standalone" litedram couldn't be provided by an internal data_width converter, and be whatever width you ask for

01:13 <somlo> I just haven't kept up with the code base, so I can't immediately point at where in litedram that would happen...

09:07 <_florent_> Finde: for now with the standalone LiteDRAM generator, the user port swill use native controller's data_width, in the future we could add data_width adapters support (which is already possible when LiteDRAM is used directly with LiteX)

11:33 <acathla> In litescope/software/driver/analyzer.py there is a self.trigger_enable.write(0) but trigger_enable does not exist somewhere else.

11:35 <acathla> I was trying to use litescope for the first time following https://github.com/timvideos/litex-buildenv/wiki/Notes-and-Tips but may be it's not up to date.

11:35 <tpb> Title: Notes and Tips · timvideos/litex-buildenv Wiki · GitHub (at github.com)

13:39 <keesj> acathla: perhaps that your csr.csv needs to be generated again?

13:40 <keesj> the pc side client code parses this file and adds the magic

13:45 <acathla> It's a freshly generated csv...

13:46 <acathla> self.trigger_enable.write(0), AttributeError: 'LiteScopeAnalyzerDriver' object has no attribute 'trigger_enable'

14:19 <acathla> keesj, you were right, it's a csr.csv problem. It's path must be specified again when calling LiteScopeAnalyzerDriver()

14:19 <_florent_> acathla: can you provide your csr.csv and/or analyzer instance?

14:22 <acathla> _florent_, it's fixed for now. But may be adding an error when default csr.csv is not found would be nice

14:23 <_florent_> acathla: ok thanks, can you create an issue on LiteScope repo for that?

14:23 <acathla> I'll try

14:38 <acathla> _florent_, done : https://github.com/enjoy-digital/litescope/issues/15

14:38 <tpb> Title: Missing csr.csv does not trigger an explicit error in LiteScopeAnalyzerDriver · Issue #15 · enjoy-digital/litescope · GitHub (at github.com)

14:43 <_florent_> thanks

15:10 <acathla> _florent_, I made a mistake, correcting it...

15:59 <Finde> thanks _florent_ that answers my question

15:59 <Finde> probably preferable for us to have the native width atm anyway

16:20 <_florent_> xobs: hi, i have a good candidate for the UART crossover over Etherbone with https://twitter.com/enjoy_digital/status/1220004677217144834, i hacked a quick python script to get the UART TX, but would like to test with wishbone-tool. I installed wishbone-tool, but was not sure if my usecase was already supported: The board is at 192.168.1.50 with Etherbone + a CPU using the crossover UART, how could i use wishbone-tool

16:20 <_florent_> to interact with the UART?

16:27 <mithro> _florent_: Should work pretty easily!

16:30 <_florent_> mithro: great, do you have an idea of the command to use? :)

16:30 <mithro> _florent_: With wishbone tool?

16:30 <_florent_> yes

16:33 <mithro> `./wishbone-tool --serial /dev/ttyUSB1 --server terminal --csr-csv ~/github/timvideos/litex-buildenv/build/ice40_hx8k_b_evn_base_vexriscv.minimal+debug/test/csr.csv`

16:34 <_florent_> ok thanks, i'll adapt that to test over etherbone

16:52 <mithro> _florent_: Have you seen https://www.ohwr.org/project/svec/issues/60 ?

16:52 <tpb> Title: V3 - Replace DDR3 memory by DDR3 SO-DIMM module (#60) · Issues · Projects / Simple VME FMC Carrier SVEC · Open Hardware Repository (at www.ohwr.org)

16:53 <mithro> _florent_: You doing any work with CERN?

16:54 <keesj> all sounds so cool

16:56 <_florent_> mithro: no, haven't seen this, thanks for the link. I've only helped a bit some people that wanted to try it at CERN

16:57 <mithro> They have been doing a bunch of Fomu workshops...

16:57 <mithro> _florent_: I also have a bunch of Colorlight 5A-75B here...

16:57 <mithro> What are you using for the JTAG interface?

17:01 <mithro> Hey rohitksingh

17:01 <rohitksingh> mithro: Hi! :)

17:03 <_florent_> mithro: i'm using https://shop.lambdaconcept.com/home/25-jtagserial-pack.html, but it should work the others FTDI based jtag cables (HS2, etc...)

17:03 <_florent_> rohitksingh: hi :)

17:04 <rohitksingh> _florent_: Hi :D

17:50 <mithro> _florent_: Did you see https://github.com/litex-hub/linux-on-litex-vexriscv/pull/71/files ?

17:50 <tpb> Title: Conda environment + Travis CI support by mithro · Pull Request #71 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)

17:51 <_florent_> mithro: yes i saw that, thanks

17:52 <_florent_> are you also planning to build the bitstreams with it?

17:52 <mithro> _florent_: Next step is to get gateware being built for ECP5

20:06 <scanakci> thank you @somlo. I just checked the width and it is 256 :). I will debug with L2 then.