03:37 <xobs> Yeah, I do have /dev/ptmx in WSL, but I'm not sure if that's available in Windows-land.

06:47 <keesj> from the link I send yesterday it was introduced in windows 10 insiders preview SDK (I normally don't run windows but go quite exited by wsl)

06:53 <xobs> Hey, is anyone running Linux on RISCV?

06:54 <xobs> I'm curious what happens when you attempt to write to SATP from User mode. I'm using Renode, and the write succeeds and disables the MMU, which seems wrong, but I haven't yet found out what it's supposed to do.

07:07 <xobs> Ah, it looks like it should raise illegalAccess: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L1040

07:07 <tpb> Title: VexRiscv/CsrPlugin.scala at master · SpinalHDL/VexRiscv · GitHub (at github.com)

07:38 <xobs> Even though it doesn't in Renode.

07:39 <xobs> So does anyone have a Linux handy that's running on Vex? I've got a simple program that should crash. Under Renode it takes down the whole system, but I suspect that's a bug.

08:00 <CarlFK> xobs: what's vex?

08:00 <xobs> CarlFK: vexriscv

08:00 <xobs> I'm trying to get verilator to work now so I can test it out. Seems like the perfect usecase.

08:01 <CarlFK> ah no.

10:38 <_florent_> xobs: not sure if that can be useful, but in linux-on-litex-vexriscv, we have a simulation (using verilator) that can boot Linux with VexRiscv: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/sim.py

10:38 <tpb> Title: linux-on-litex-vexriscv/sim.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)

10:39 <_florent_> https://github.com/litex-hub/linux-on-litex-vexriscv#running-the-litex-simulation

10:39 <tpb> Title: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com)

10:59 <xobs> _florent_: thanks, that might help! I'm working to get something working in Verilator, but having Linux would help too.

15:07 <xobs> _florent_: huh. That seems like unintended behavior. I ran that program in that simulator, and it quit verilator.

15:19 <xobs> Ah, no, that's probably expected when it gets an illegal instruction.

15:23 <_florent_> xobs: yes, the CPU is probably writing the finish CSR on illegal instruction to stop the simulation

15:37 <xobs> Right. Whereas with Renode, it actually gets stuck in user mode and the PC jumps to an invalid offset. Also, Renode will happily read satp all day. Currently starting verilator to see what happens if I try the same program there. I suspect it'll crash, too.

15:38 <sorear> xobs: it should raise illegal instruction, not an access/page fault

15:39 <sorear> basically everything in riscv is an illegal instruction unless there’s more specific handling

16:25 <xobs> sorear: yeah, that's what I see under Verilator, but not under Renode: `CPU Exception: Illegal instruction 0x18002573 at 0x2050020c`

16:27 <sorear> renode seems buggy with exceptions