_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
<sajattack[m]> I figured out how to fill the rest of the screen all by myself 😛
<sajattack[m]> s/57/80
<sajattack[m]> s/19/29
<sajattack[m]> maybe it should be 79
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<sajattack[m]> it's me :)
<sajattack[m]> if you look closely at the reflections in the tv you can see my pajama pants and recycling lmao
<futarisIRCcloud> DE10 Nano and the mister project is great. I've seen some great reversing of classic arcade systems from:
<futarisIRCcloud> jotego (@topapate): https://twitter.com/topapate
<sajattack[m]> jotego is a bit of a lone wolf dev. He uses a modified mister framework and holds beta cores for ransom on his patreon
<sajattack[m]> I like alan, sorg, and rysha
<sajattack[m]> jotego's just not as cooperative and open source friendly as everyone else
<awygle> given that litex streams have records as their payloads, how do things like the Gearbox work when going from wide->narrow? do you put the records back together on the "other side"? do records have a defined mapping to signals?
<sajattack[m]> ayy, digital design hq gang
<awygle> Oh lol, hey
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<_florent_> awygle: the current gearbox is operating on raw data, if you want to pass a record to it you need to use raw_bits() or do the signal mapping in the design.
<acathla> Does somebody have an example of using spibone, remote side? xobs?
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