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sajattack[m]>
does migen have an equivalent to verilog's thing where you can assign something multiple times and the last one will take precedence?
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awygle>
er, sorry. thought i was in #nmigen and autocompleted an "n" there. no idea about migen lol
<
sajattack[m]>
ok well I hope it does
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john_k[m]>
It does
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dkozel>
Hi
_florent_ You offered a few weeks to give some guidance on getting my Aller PCIe board up and running with LiteX, could use that help now
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dkozel>
Board is in and seems to be detected, LiteX and everything else is up to date, and I've built the demo image
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dkozel>
buut... ha, not sure if I even can program it over PCIe or if I need to get the JTAG interface up.
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_florent_>
dkozel: hi, sure i can try to help
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_florent_>
so the board is detected with lspci?
<
dkozel>
03:00.0 Memory controller: Xilinx Corporation Device 7024
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_florent_>
i'm going to look at the Aller target just to see what it does and what you can test
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_florent_>
have you already programmed it with the LiteX design or is it the default configuration?
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dkozel>
Default config
<
dkozel>
I don't know how to program it (short of the JTAG adapter, which I don't have yet)
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dkozel>
Reading app notes makes it sound like it could/should be possible
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_florent_>
ah ok, i'm not well aware of what is already loaded to the board
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_florent_>
i would recommend using using/having a JTAG cable
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dkozel>
Yeah, I've ordered one from Digilent, not sure what their shipping is like at the moment
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dkozel>
bit of an oversight
<
dkozel>
I'll ping Numato and see if they have a suggestion, otherwise catch you back here in a few weeks
<
tpb>
Title: GitHub - enjoy-digital/netv2: NeTV2 SoC based on LiteX (at github.com)
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_florent_>
i'll take the time to do it in the next days
<
_florent_>
please ping me when you know how to reprogram your board and i'll help you getting LitePCIe working
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dkozel>
Thanks. What's useful about that netv2 based design?
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_florent_>
That's just that i know i tested/updated it recently and the software is included
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dkozel>
Ok, sounds great. I'll let you know when I have more pieces here. Thanks
<
dkozel>
My core interest is DMAing data over PCIe to one or more blocks hanging of the wishbone bus or similar, then back up to the host.
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dkozel>
If that helps narrow what bits of the design are most relevant
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_florent_>
ok, i can easily create a design with that
<
dkozel>
Many thanks. I'm looking forward to learning more gateware dev. Almost all of what I've done is debugging DSP inside of existing designs.
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pdp7>
trying the orangecrab and getting:
<
pdp7>
build_top.sh: line 4: /opt/Diamond/diamond_env: No such file or directory
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pdp7>
Is Diamond the lattice ide?
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pdp7>
ah ok... i didn't need for the other ECP5 boards
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somlo>
interesting, the default toolchain is "trellis" in the latest litex-boards git version
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somlo>
i.e. yosys/trellis/nextpnr
<
tpb>
Title: litex-boards/orangecrab.py at master · litex-hub/litex-boards · GitHub (at github.com)
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somlo>
pdp7 any chance your litex-boards repo is a few commits behind the latest?
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somlo>
alternatively, try "--gateware-toolchain trellis"
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gregdavill>
Yep, the old default on the orangecrab was diamond, it's now been updated to Trellis.
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pdp7>
Thanks all. I can build the gateware now
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rjeschmi>
I'm having a tough time with LiteEth and understanding the clocks. They seem to get renamed on me when I make changes.
<
rjeschmi>
for a while they were eth_rx and eth_tx
<
rjeschmi>
but now they are eth_clocks_tx and eth_clocks_rx
<
rjeschmi>
Is this something to do with AutoCSR? Or is there something I'm missing?
<
rjeschmi>
which is only a problem when it tried to compile and eventually gets to: ERROR:ConstraintSystem:59 - Constraint <NET "eth_rx_clk" TNM_NET =
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rjeschmi>
"PRDeth_rx_clk";>
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