_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<tpb> Title: soc: add add_constant/add_config methods · enjoy-digital/litex@3ba7c29 · GitHub (at github.com)
<esden> The commit message does not seem to be related to that class disappearing as far as I understand.
<esden> If that was intentional what is the replacement for SoCMemRegion?
<esden> Just to clarify this is what I am trying to build again. It did work only two weeks ago or so. :( https://github.com/esden/litex-boards/blob/icebreaker/litex_boards/targets/icebreaker.py#L203
<tpb> Title: litex-boards/icebreaker.py at icebreaker · esden/litex-boards · GitHub (at github.com)
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<levi> Looks like it's the add_memory_region and similar methods here: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L215
<tpb> Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com)
<levi> I am not sure; I ran into some similar issues trying to get a board updated to work with the latest litex after getting started in litex-buildenv
<tpb> Title: GitHub - SymbiFlow/prjxray-bram-patch: Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams. (at github.com)
<mithro> bunnie[m]: You might be interested in the above too....
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<mithro> Was written by a student and still a WIP, so don't expect too much
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<xobs> That's cool! I know that's one of the huge pain points for people doing FPGA work.
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<bunnie[m]> ooh cool
<bunnie[m]> ah yes...the patch loop going through fasm intermediate representation. neato!
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<_florent_> esden: SoCMemRegion was supposed to be used internally (but that's true it was not specified anywhere), i'll look at your design and update it
<esden> no worries I have removed that
<_florent_> mithro: nice tool, that will indeed be very useful
<_florent_> esden: so have you been able to fix your design?
<esden> not sure if I still have to deal with the memory stuff or not maybe for gdb?
<esden> xobs: helped me a bunch to navigate the api changes and stuff
<esden> also I had to disable the bios building as it is waaaaay too large
<_florent_> esden: i think you were using these two lines to define a memory region that is only used by the linker
<esden> so I am back to doing the jump to my program immediatly trick that xobs has as the bios is useless for me anyways
<esden> I really wish litex was bit less in "flux" let's say. It was really hard to get things to work again. :(
<esden> but it blinks now and I can write a c program for it which is very nice
<esden> but I do have a bit of a feeling that I am shooting with a bazooka at a fly here :D
<esden> but having the csr headers autogenerate is nice
<esden> Thanks for explaining the line. You are probably right, the linker script does not look right to me. I had to change the definitions by hand when I was copying out the autogenerated files into my C project.
<_florent_> yes sorry for the changes, we should really specify what is for internal use / what is the user API. I'm generally trying to provide retro-compatibility for the API, but that's more difficult when users are using internal elements of LiteX.
<esden> I need to tidy things up and hopefully will be able to submit a pull request at least with the icebreaker platform file.
<esden> Yeah of course. The internal API stuff was not the only issue though. :)
<esden> the change of the csr access function name threw me off too.
<_florent_> esden: if you want to define a linker region, you can do it with add_memory_region, similar to: https://github.com/timvideos/litex-buildenv/blob/master/targets/ice40_up5k_b_evn/base.py#L103-L105
<tpb> Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com)
<esden> and that the bios became suddenly massive
<esden> I was trying to do it "the intended way" but had to disable the bios completely to move forward.
<esden> Ohh great, thanks for the link. I will look at it. :)
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<_florent_> esden: BTW, i have an iCEBreaker board and could help more if needed. If you do a PR with your iCEBreaker design to litex-boards, i could maintain it and make sure it still build with Travis-CI.
<_florent_> esden: so before the changes, you were able to use the LiteX Bios with the iCEBreaker and it's no longer the case?
<esden> Awesome! Yeah it was definitely a plan from the beginning to send the stuff up stream to you. :)
<esden> Yeah before the recent changes it was fitting, barely but it was fitting.
<esden> At the end still not very useful as I don't really need or want it. I rather have the space available for the application. :)
<esden> It was more of an excercise to see that we got the SoC to work and are able to use the build system to create a working binary.
<esden> Much more useful would be generating of a "C project skeleton".
<_florent_> That would be good to have it working, and when space it needed (which is generally the case with iCE40 :)) the BIOS could be moved to the SPI Flash
<esden> Also I think xobs said that him disabling the bios and just forcing the 4 byte jump to application thing is not the intended way to do it and a bit of a hack.
<esden> Ohh the bios was in SPI flash all the time.
<esden> there is no way in hell it would ever fit onto the ICE40
<_florent_> ah ok, then there is no reason it's no longer possible
<_florent_> if i want to help, should i use https://github.com/esden/litex-boards/tree/icebreaker? or do you have something you already updated?
<tpb> Title: GitHub - esden/litex-boards at icebreaker (at github.com)
<esden> well I say "no way" there are always ways and means. But it was not fitting on the ice40 earlier either.
<esden> I have done some work over here. I have not pushed it yet.
<esden> I need to clean up the mess I made. :)
<esden> I will be pushing it to the icebreaker branch you pointed out though.
<esden> I will let you know as soon as I have done so. :)
<_florent_> ok, i'm just going to do a quick test with the old files to see
<esden> _florent_: will add_mem_regions overwrite the setting for a region if called a second time on the same name of a region?
<_florent_> it should produce an error if you use the same name
<_florent_> telling you that is has already been defined
<esden> ok, well that is the point why xobs used the other method to access it. We need to override the default.
<esden> ok rebased and force pushed updated files to my branch
<esden> Keep in mind that the address where the bios in the flash is at the moment is not compatible with the master iceprog.
<esden> iceprog by default deletes bigger pages so you need to use the newly added `-i 4` option that I added in this pull request when flashing the bios at the 0x0001a000 address. Or you need to move the bios to 0x00020000 and waste some more flash space. :) https://github.com/cliffordwolf/icestorm/pull/247
<tpb> Title: Added an option to choose the erase block size. by esden · Pull Request #247 · cliffordwolf/icestorm · GitHub (at github.com)
<esden> Ohh I just realized, the bios probably is overrunning now because I could not override the rom block size in the linker script... duh...
<esden> Ok, here is what I have so far regarding wishbone-tool and LED blinking. https://github.com/icebreaker-fpga/icebreaker-litex-examples
<tpb> Title: GitHub - icebreaker-fpga/icebreaker-litex-examples: Example litex Risc-V SOC and some example code projects in multiple languages. (at github.com)
<esden> _florent_: I can create a pull request from my icebreaker branch if you want. Unless you have some suggestions and want me to tweak and clean things before I do that.
<_florent_> esden: yes sure, that will be probably be easier. You can do that, then we could merge and i will test/update it if needed.
<_florent_> esden: so from what i understand, with your target you want to be able to create a minimal SoC with a CPU or with the UART bridge?
<esden> Yeah the goal is to get a bare bones CPU that I can program in C, Rust, Micropython. That can have some gpio or some some other fun cores connected to the icebreaker Pmods.
<esden> I have sent in the pull request: https://github.com/litex-hub/litex-boards/pull/51
<tpb> Title: Add iCEBreaker FPGA support by esden · Pull Request #51 · litex-hub/litex-boards · GitHub (at github.com)
<esden> there is also a link to the example code I mentioned above.
<esden> The overarching motivating project is the TWANG game port to the icebreaker.
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<_florent_> Thanks for the PR, it's merged. I'll play with it in the next days and see if i can get the BIOS working again.
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<sajattack[m]> turns out having fpgas close amplified dodgy rca is a bad idea
<sajattack[m]> * turns out having fpgas close to amplified dodgy rca is a bad idea
<mithro> esden: BTW the bios should have gotten smaller again. The bios size increase was reverted and LTO has been enable which gives somewhere between 10% and 40% depending on your configuration
<esden> _florent_: awesome thank you for merging! :)
<esden> mithro: ok that is nice. :) But first, after thinking about it I don't think the problem here was the actual size increase but the fact that I had to disable the linker rom address remap. And second, I don't really need the bios. It would be nicer if we could have a way to provide an alternative demo program as part of litex. The bios functionality is not really useful on tiny boards like the iCEBreaker or Fomu. :)
<esden> in this case we just want the bare metal and header definitions so we can program it like a small microcontroller.
<esden> That said I am glad I can finally write some C programs for it. It took long enough to get here.
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