14:11 <acathla> _florent_, I'm lost. There are many more signals on MIIs, I don't know which module to keep or not...

14:13 <_florent_> acathla: maybe the best is to look at GMII, since the PHY is also 8-bit: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/gmii.py

14:13 <tpb> Title: liteeth/gmii.py at master · enjoy-digital/liteeth · GitHub (at github.com)

14:14 <_florent_> you need to create equivalents of https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/gmii.py#L12-L43 for TX and RX

14:14 <tpb> Title: liteeth/gmii.py at master · enjoy-digital/liteeth · GitHub (at github.com)

14:14 <_florent_> for the CRG, you can just create a dummy one using sys_clk for the eth_clk

14:14 <acathla> _florent_, ok.

14:15 <_florent_> acathla: in fact, sorry you should probably look at https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/model.py

14:15 <tpb> Title: liteeth/model.py at master · enjoy-digital/liteeth · GitHub (at github.com)

14:15 <_florent_> you can just reuse this CRG

14:15 <acathla> I was just looking at it =)

14:16 <_florent_> and you can find the connection needed here: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/model.py#L36-L48

14:16 <tpb> Title: liteeth/model.py at master · enjoy-digital/liteeth · GitHub (at github.com)

16:09 <acathla> _florent_, is the LiteEthPHYModel supposed to be a loopback interface? I see no Tx or Rx

16:20 <_florent_> acathla: there is no TX/RX because it's directly done in the model

16:20 <_florent_> https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/model.py#L36-L40 is the TX

16:20 <tpb> Title: liteeth/model.py at master · enjoy-digital/liteeth · GitHub (at github.com)

16:20 <_florent_> https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/model.py#L36-L40 is the RX

16:39 <acathla> _florent_, where does those pads.source_valid and pads.sink_valid go? I'm lost again :(

16:40 <_florent_> acathla: that's a record from https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_sim.py#L51-L57

16:40 <tpb> Title: litex/litex_sim.py at master · enjoy-digital/litex · GitHub (at github.com)

16:41 <acathla> SocCore is using LiteEthPHY which will choose the right LiteEth*MII which will use LiteEthPHY*MIICRG and TX/RX

16:42 <acathla> _florent_, Oh, ok, so I can generate these signals from my own module

16:43 <_florent_> yes

16:43 <_florent_> if you want to be sure to use the right PHY, you can also avoid using LiteEthPHY and just replace this with your PHY