_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<mithro> FYI - whitequark reminded me that nmigen chatter has moved to the #nmigen channel
<sajattack[m]> would linux on litex run with only 8MB sdram?
<levi> Been a long time since that small of a system was a common target. I wouldn't bet on it, but it may be possible. You certainly used to be able to, though.
<sajattack[m]> ok
<_florent_> sajattack[m]: 8MB it will work with LiteX, but if you want to run Linux on it, the minimum supported is currently 32MB
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<rvense> i have technically run linux recently on 8mb ram (stm32f7) but not done much with it
<Claude> hi, i struggle a bit to instance a verilog module into my target. i added "self.platform.add_source("/home/claude/gateware/i2c_top.v") . but it seems to me that litex/nmigen cant find the module
<Claude> thats the output i get https://pastebin.com/94dNKXnp
<tpb> Title: Traceback (most recent call last): File "./make.py", line 363, in - Pastebin.com (at pastebin.com)
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<Xiretza> Claude: paste the whole source
<tpb> Title: [Python] #!/usr/bin/env python3 # This file is Copyright (c) 2018-2019 Florent Kermarr - Pastebin.com (at pastebin.com)
<daveshah> Claude: try platform.add_source not self.platform.add_source
<Claude> ok thanks will try
<Claude> i'm obviously a python idiot ;)
<Claude> daveshah: thanks that looks good now
<Xiretza> Claude: yeah, that. `platform` is only passed as a function argument to __init__, it's not a member variable
<Claude> nice thanks for the help :) that works now. somehow i thought its a good idea to put a pll chip on my board which needs an i2c init first before it outputs clocks. but somehow i forgot to connect an always enabled clock to the fpga. so the i2c stuff iÄm doing is a small verilog init of the pll chip, prior the fpga PLLs get their reset and lock to the now incoming clock
<Claude> yay , boots now very reliable. prior i was using the OSCG as input to the FPGA PLLs. was quite unstable on the uart upload. now i can add my hdmi phy (TDA19888) and try running linux with framebuffer
<Claude> TDA19988 even..
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