_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<tpb> Title: litex/nexys4ddr.py at master · enjoy-digital/litex · GitHub (at github.com)
<somlo> How does it actually still work on other targets where this isn't done? :)
<_florent_> somlo: for most of the ethernet PHYs in LiteEth, the clocks are coming directly from the chip and clock domains created in the PHYs. For the RMII PHY, the FPGA generate a 50MHz clock to the chip and this clock is also used in the PHY for TX/RX.
<somlo> oh, ok, so these three boards all use rmii.py, and every other target uses something else
<somlo> thanks, that makes sense now :)
<_florent_> somlo: yes that's indeed specific to RMII PHYs
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<awygle> is liteeth a submodule of litex or something? the test suite is failing because i don't have liteeth installed
<awygle> same for litedram
<sajattack[m]> if you run litex_setup.py it will fetch all the submodules and install them
<awygle> i guess more generally, "what is the best way to get set up to develop on litex (not with it)?"
<sajattack[m]> in the litex repo
<awygle> but a) i want to work on the source directly and b) i want to install them in a venv, surely?
<sajattack[m]> I didn't bother with a virtualenv, it will fetch them all as submodules and you can change stuff and re-run setup.py
<sajattack[m]> that's what I do
<sajattack[m]> but I'm not an expert
<awygle> mmk, guess i'll just roll with it. what's the worst that could happen.
<daveshah> I think litex_setup.py uses "develop" so changes to the repo don't need to be installed
<awygle> seems like it yeah
<sajattack[m]> if all else fails clone all the repos
<awygle> when the litedram test suite says its looking for "any of the cross-compilation toolchains", what does it want specifically? gcc and binutils?
<daveshah> Yes
<awygle> mk thanks
<daveshah> It doesn't need any libraries as it provides its own compiler_rt
<daveshah> So pretty much any RISC-V gcc, even a Linux one, should suffice
<awygle> cool
<awygle> hm, just installing the package from ubuntu does not seem to work unfortunately
<daveshah> What prefix are those?
<awygle> riscv64-linux-gnu
<daveshah> Ah, looks like it only looks for riscv64-linux not riscv64-linux-gnu in the list
<awygle> the list of toolchains it's looking for includes "riscv64-linux", yeah
<awygle> to crosstool-ng i spose :p
<tpb> Title: litex/.travis.yml at master · enjoy-digital/litex · GitHub (at github.com)
<sajattack[m]> you can also edit the list of accepted toolchains
<awygle> arright there we go, pass
<awygle> now how to run the example....
<awygle> Oh, are the litedram examples just examples of dram config that need to be included in larger examples like the litex ones?
<daveshah> No, litedram can also generate a "standalone" core using those yaml files
<daveshah> Although the standalone core is effectively a whole LiteX SoC (CPU needed for the init) with a DRAM slave port exposed
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<awygle> i just want to run a thing that loads onto the versa board, runs some kind of RAM self-test, and then says 'yay' or 'nay' over serial or blinkenlight
<daveshah> Using a LiteX target rather than litedram would be easier
<sajattack[m]> the litex bios has memtest built in
<awygle> do i just cd into litex/boards/targets and python3 versa_ecp5.py?
<daveshah> Running https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/versa_ecp5.py will create you a bitstream that prints memory test result to the UART at 115200
<daveshah> yes
<tpb> Title: litex/versa_ecp5.py at master · enjoy-digital/litex · GitHub (at github.com)
<awygle> cool, thank you
<sajattack[m]> yeah and then lxterm something or other
<daveshah> Or any other serial terminal (I think the line end issue is solved now so any terminal works)
<awygle> litex seems fairly... inseparable?
<awygle> like it seems difficult to use only small bits of it
<awygle> is that fair?
<daveshah> Well if you don't mind having a whole SoC just for DRAM init it is quite possible to use litedram standalone
<daveshah> liteeth has a less heavyweight standalone mode
<awygle> i see
<_florent_> awygle: the "issue" with a DRAM controller is that you need to do the initialization and as soon as you need to do read/write leveling (for DDR3, DDR4) it's often easier (and even cheaper in resource usage) to have a full SoC than the logic to do that. For now we are using the lite variant of VexRiscv for that, but we could probably reduce resource usage with a slower/smaller CPU. So for this kind of core, the
<_florent_> standalone version is indeed a full SoC.
<somlo> awygle: here's how I set up my entire environment: http://www.contrib.andrew.cmu.edu/~somlo/BTCP/#sec_2_2
<tpb> Title: A Trustworthy, Free (Libre), Linux Capable, Self-Hosting 64bit RISC-V Computer (at www.contrib.andrew.cmu.edu)
<somlo> ignore the git commit IDs and go with the latest (also adjust for non-Fedora distros in terms of installing packages), but that's it for me in a nutshell
<awygle> thanks!
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<somlo> being relatively new to Python, I really like how "python3 setup.py develop --user" installs links (in $HOME/local/lib/...) pointing at my git repos, and I can keep hacking on them without needing to reinstall anything
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