_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<lambda> how does the native interface for litedram work? there's the cmd_ signals, which I assume are used to start a transaction, but how do they relate to wdata? they have separate _ready signals, do both have to be asserted to start a write?
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<lambda> or, if they're independent, what are the maximum delays between the two?
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<_florent_> lambda: you have 3 streams: cmd/wdata/rdata, cmd is used to pass the write/read addresses. When you present the write cmd on cmd, you also need to provide the write data on wdata. If you present a read cmd on cmd, you must be sure rdata interface will be able to accept the return data. The dma frontend module can help you understand it. It's also possible to expose an AXI port if that's easier for you.
<lambda> _florent_: I'll have a look at the DMA. The thing I'm still wondering about: is it possible for cmd_ready to be asserted while wdata_ready isn't? And if so, do I have to wait for the write stream to become available before issuing the write command?
<_florent_> yes for a write you'll have cmd_ready asserted before wdata_ready. But since the delay between cmd_ready and wdata_ready is unknown (it depends of the internal state of the DRAM, if the row already open, etc...), i would recommend setting wdata when issuing the command.
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