_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
spacekookie_ has joined #litex
st-gourichon-f has joined #litex
karol has joined #litex
pbinkowski1 has joined #litex
spacekookie has quit [Ping timeout: 268 seconds]
nn_ has joined #litex
st-gourichon-fid has quit [Ping timeout: 240 seconds]
kgugala has quit [Ping timeout: 240 seconds]
pbinkowski has quit [Ping timeout: 240 seconds]
rvense has quit [Ping timeout: 240 seconds]
_whitelogger has joined #litex
spacekookie has joined #litex
kbeckmann2 has joined #litex
spacekookie_ has quit [*.net *.split]
kbeckmann1 has quit [*.net *.split]
_whitelogger has joined #litex
_whitelogger has joined #litex
_whitelogger has joined #litex
HEGAZY has joined #litex
nn_ is now known as rvense
karol is now known as kgugala
scanakci has quit [Quit: Connection closed for inactivity]
<somlo> so, after RTFMing a bit on the "mmcme2_adv" and "dcm_clkgen" blocks from xilinx, it doesn't look like "ehxplll" on ecp5 can set up for a progammable output frequency
<somlo> which means that on ecp5 we'll have a hardcoded sdcard clock that won't be software-adjustable
<daveshah> Yeah, there's no real programmability
<somlo> on the bright side, it should be simple to set up for this n00b :) Downside being it won't be as awesome as it is on xilinx...
<somlo> going completely off on a tangent, I don't quite understand the point of an adjustable sdcard clock frequency -- why not just pick the largest value that makes sense (as close to 50MHz as possible) and enjoy? :) I'm sure I'm missing something, but I don't know what...
<somlo> this might be a question for _florent_, if/when he checks his IRC backlog...
<_florent_> somlo:the SDCard initialization need to be done at a low frequency. The current clocker module is using a PLL, because i wanted to evaluate the max frequency we were able to achieve, but we could have something that just has 1 clock and a clock divider for the initialization.
<somlo> _florent_: by "SDCard initialization" do you mean running the sdcard_init() routine in the bios, or something else that happens in the gateware?
HEGAZY has quit [Quit: Konversation terminated!]
HEGAZY has joined #litex
CarlFK has quit [Ping timeout: 256 seconds]
HEGAZY has quit [Quit: Konversation terminated!]
<Claude> Sounds like bios , because the actual card initialisation must indeed with maximum 400khz card clock
<Claude> After that init the card answers back the highest frequency it supports
<Claude> Or one can ask the card .. better said
CarlFK has joined #litex
<somlo> Claude: then the "set-clock -> init -> test" sequence here: https://github.com/enjoy-digital/litesdcard/blob/master/README#L82 is probably not telling the whole story
<tpb> Title: litesdcard/README at master · enjoy-digital/litesdcard · GitHub (at github.com)
<somlo> we set the sd clock to 10MHz, initialize, then test. I've successfully set the clock to 50, initialized, and tested :)
<somlo> seems like it should be 1. set clock to 10MHz; 2. init; 3. set clock to maximum (as per card init results; 4. test/use/whatever
<somlo> anyway, for now I'll try to get ecp5 working with a 10MHz fixed clock, then we can add the option to switch to something faster later down the road
<somlo> one more thought/question: I was able to successfully run sdinit on all my cards (even the ones that subsequently failed the test), and I was able to successfully sdinit them all at *any* frequency from 10 through 50 MHz
<somlo> is that just the cards being permissive, but not something I should rely on (per the sdcard specs, which I have admittedly *not* read)? :)
CarlFK has quit [Ping timeout: 255 seconds]
kbeckmann2 is now known as kbeckmann
kbeckmann has quit [Quit: WeeChat 2.7]
kbeckmann has joined #litex
CarlFK has joined #litex
<awygle> cards are usually fine with initialization at whatever frequency, but it's technically in violation of spec to ask them to be.
<awygle> you're supposed to come up in "compatibility' mode which is <400 kHz clock iirc
awygle has quit [Remote host closed the connection]
awygle has joined #litex
<somlo> awygle: yeah, that was my guess, thanks for confirming!
<awygle> as florent said what we usually do is run a max-rate clock and a clock divider. All internal logic runs at max-rate, the divider only affects the output.