_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
CarlFK has quit [Quit: Leaving.]
CarlFK has joined #litex
rohitksingh has quit [Ping timeout: 260 seconds]
_whitelogger has joined #litex
rohitksingh has joined #litex
gregdavill has joined #litex
rohitksingh has quit [Ping timeout: 240 seconds]
CarlFK has quit [Quit: Leaving.]
rohitksingh has joined #litex
gregdavill has quit [Ping timeout: 256 seconds]
gregdavill has joined #litex
gregdavill has quit [Ping timeout: 240 seconds]
gregdavill has joined #litex
CarlFK has joined #litex
rohitksingh has quit [Ping timeout: 256 seconds]
m4ssi has joined #litex
_whitelogger has joined #litex
gregdavill has quit [Ping timeout: 256 seconds]
HEGAZY has joined #litex
m4ssi has quit [Remote host closed the connection]
m4ssi has joined #litex
HEGAZY has quit [Remote host closed the connection]
HEGAZY has joined #litex
rohitksingh has joined #litex
m4ssi has quit [Remote host closed the connection]
HEGAZY has quit [Read error: Connection reset by peer]
rohitksingh has quit [Ping timeout: 240 seconds]
HEGAZY has joined #litex
gregdavill has joined #litex
<scanakci> is it possible to use VCS when simulating a core with LiteX instead of verilator?
gregdavill has quit [Ping timeout: 256 seconds]
gregdavill has joined #litex
rohitksingh has joined #litex
rohitksingh_ has joined #litex
rohitksingh has quit [Ping timeout: 265 seconds]
HEGAZY has quit [Quit: Konversation terminated!]