_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<mithro> _florent_: Morning
<mithro> _florent_: Where are we at with the litex pythondata stuff? I think we just need to solve the tapcfg issue?
<tpb> Title: Support multicore configurations · Issue #85 · SpinalHDL/VexRiscv · GitHub (at github.com)
<tpb> Title: Migrate from travis-ci.org to travis-ci.com · Issue #180 · enjoy-digital/litedram · GitHub (at github.com)
<Finde> Huh with write-through invalidations that would fit P-Mesh pretty well...
<_florent_> sorry in a meeting
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<_florent_> mithro: hi, for the pythondata, yes i think the only remaining thing is the tapcfg issue
<_florent_> sorry i've not been able to look at it yet
<_florent_> great for the SMP with Vexriscv :)
<mithro> _florent_: I'll probably look at the tapcfg thing shortly
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