_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<zyp> hmm, I just realized that the first/last mechanism of the streams doesn't support signalling a zero length packet
<_florent_> zyp: can you describe what you want to achieve?
<zyp> I'm currently trying to reuse LiteEthMACCRCInserter for usb (with a suitable CRC16 class), and in the case of a zero length packet, the output should consist of only the two crc bytes
<_florent_> ok, LiteEthMACCRCInserter is indeed probably expecting at least a data, you could use a modified version that would only insert the CRC is there is no data (you could add a be or length field to the payload to indicate data validity).
<zyp> yeah, I just realized that this is gonna be a problem all over the place, not just for CRC
<_florent_> this signaling indeed needs to be added by the user as a payload parameter
<zyp> length field sounds like a good idea, that'll also be useful later to increase the datapath width
<zyp> so a zlp will be signalled by first=1, last=1, length=0
<zyp> by the way, is there any documentation on the stream api anywhere? I'm still a bit uncertain how the timings are supposed to work
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<shuffle2> agree
<shuffle2> i suspect everything is just yolo'd, so you have to read how any pre-existing code expects to use the stream
<zyp> I figured it out, I just misread some code that led me to doubt that my understanding was correct
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<_florent_> it could be better, but there is this: https://github.com/enjoy-digital/litex/wiki/Streams
<tpb> Title: Streams · enjoy-digital/litex Wiki · GitHub (at github.com)
<_florent_> the streams are basically a simplified AXI (valid/ready/first/last/payload/param) that you can customize depending the need/project
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