_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<benh> _florent_: a couple of PR should be in your inbox (litex and litedram)
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<benh> _florent_: the cpu_none tests in Travis failed, not sure what's up there, I have never used the test stuff yet
<_florent_> benh: thanks for the PRs, i'll look at the tests while reviewing/merging
<benh> _florent_: can I run those tests locally ?
<benh> ok thanks
<_florent_> to run them locally: python3 setup.py test
<benh> ok, time for bed but if you don't get to sort it out by my tomorrow, I'll have a look, thanks
<_florent_> i'm probably going to have a look at it now, have a good night :)
<shuffle2> i have LiteEthPHYRGMII and LiteEthUDPIPCore with default dw=8, and done eth_core.udp.crossbar.get_port with dw=16
<shuffle2> still having some misunderstanding of how stream is supposed to work, or something
<shuffle2> e.g. on the rx path, if i send udp packet with data length 12, i would expect to see 6*2bytes of data
<shuffle2> instead i see 9 pulses of valid from the converter...seems padded with zeros at the end?
<shuffle2> even tho the depacketizer has latched correct length value
<shuffle2> wireshark on the sending pc doesn't show the sender has added any padding, the stream should end after 12 bytes of data
<_florent_> there is a minimum frame size with Ethernet, it's possible the hardware of your network card is inserting padding
<_florent_> maybe you should try with a longer payload to see if you have the same behavior
<shuffle2> _florent_: ah heh, that does seem to be what's happening :)
<shuffle2> imo i/o from the "udp" level of liteeth should account for this tho?
<shuffle2> i saw before liteeth mac layer inserts padding, too bad inverse can't be done in mac for rx
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<_florent_> we could try to improve this, even if it's not possible at the MAC level, we could make sure the padding is removed at the UDP level
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<rw1nkler> Hey, is it possible to use multiple instances of serial2console in LiteX simulation? Currently, it gives me segmentation fault. I'm trying to simulate two UARTs
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