10:43 <kbeckmann> 1440p60 would have been fun but it seems I can't go above 800 MHz on the PLL, at least not using the algorithm in ecppll. Maybe it's possible to generate a PLL config that does that anyway :).

10:51 <zyp> the ecp5 pll is specced to a VCO freq between 400-800MHz, so a config generator would naturally try to keep within those bounds to generate a config valid to spec

10:53 <zyp> but if you pick your own factors, nothing prevents you from exceeding that

10:54 <zyp> things will just start acting weid once you get too far out of spec :)

10:54 <zyp> weird

14:08 <kbeckmann> zyp: thanks, I have to try it out. This is already out of spec since the output buffers are rated at 800 MHz and I use them at 1500 (!)

14:09 <tnt> Mbps not MHz.

14:09 <zyp> which output buffers? aren't they rated for 400 MHz?

14:09 <tnt> yeah 800 Mbps i.e. 400 MHz.

14:09 <zyp> I thought top/bottom banks would do 200 and side banks would do 400

14:10 <zyp> ah, because DDR, right

17:25 <loxodes> I'm trying to stream samples from an ADC into HyperRAM memory that is attached to a litex soc, do y'all have any advice on how to approach this?

17:25 <loxodes> On a board with DRAM I've used LiteDRAMDMAWriter to haul samples from a module into memory, but that doesn't support HyperRAM.

17:25 <loxodes> Is there a more general library for streaming data into memory from a module, or should I build something from scrach myself? (I'm inexperienced and mostly work by combining examples, in this case I'd be looking at wishbonebridge for writing to wishbone and LiteDRAMDMAWriter?)

17:41 <zyp> not sure if there are already any stream to wishbone dma modules, but it shouldn't be too hard making one

18:06 <_florent_> loxodes: we don't have a DMA <--> Wishbone currently, but it would indeed be useful for some use cases

18:07 <loxodes> okay, thanks!

18:07 <_florent_> loxodes: creating one similar to LiteDRAMDMAWriter but targeting Wishbone is a good idea, if you want to create it and need help, i'm happy to help