_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<shuffle2> hm, signals passed as args to add_platform_command will also be passed through vns.get_name()
<shuffle2> is there a way to express a constraint on signals in verilog (not generated from python)?
<shuffle2> vns is only the top module (right?)
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<shuffle2> oh, nvm
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