02:09 <dkozel> I don't know who might find this interesting, but I just wrapped the litepcie kernel module into dkms and the userspace into a packaged library, both with deb packages

02:17 <dkozel> _florent_: I'm going to organize my work and push up a repo tomorrow. It's definitely based on the litepcie_aller_test repo, but is going to be organized so differently I don't know that forking makes sense. Copyright and credit will definitely be all there.

02:45 <mithro> scanakci: https://github.com/litex-hub/pythondata-cpu-blackparrot/pull/1#issuecomment-622657727

02:45 <tpb> Title: update source files and organize repo by scanakci · Pull Request #1 · litex-hub/pythondata-cpu-blackparrot · GitHub (at github.com)

02:45 <scanakci> I just saw it. I think automatically updating BP is not a good idea at this point

02:46 <scanakci> Between commits, there are still drastic changes.

02:46 <mithro> scanakci: You can still pin your requirements to a specific change

02:46 <mithro> s/change/version/

02:46 <mithro> https://github.com/litex-hub/pythondata-cpu-blackparrot#using-pip-with-git-repository

02:46 <tpb> Title: GitHub - litex-hub/pythondata-cpu-blackparrot: Python module containing system_verilog files for blackparrot cpu (for use with LiteX). (at github.com)

02:47 <mithro> scanakci: Otherwise, you can send a pull request to enjoy-digital/black-parrot repo and the pythondata-cpu-blackparrot will be automatically generated

02:54 <scanakci> okay, will update the PR.

03:31 <scanakci> For now, I went with the last option. Once BP becomes stable, we can switch to main BP repo.

09:34 <john_k[m]> Skip: thanks for pushing the PanoG2 Ethernet stuff forward, I ran into the same issue when trying to enable it and kind of gave up at the time since I couldn’t get RAM working either

09:35 <john_k[m]> mithro: hah great news on the SMP front, not sure how useful 20 cores would be on the PanoG2 though! Neat to know that it could be done

11:00 <_florent_> dkozel: litepcie_aller_test has been created to give you a reference, feel free to reuse the content as you want, i'll probably remove this repository later. If you create another project, feel free to post infos here, that's always interesting to know what is done with the tools. (I would also like to explore a bit with GNU Radio, so that could be a good way to discover it).

11:06 <_florent_> dkozel: i think you could be interested by the Acorn CLE 215+ FPGA mining board: http://www.squirrelsresearch.com/acorn-cle-215-plus/

11:06 <tpb> Title: Acorn CLE-215+ | SQRL (at www.squirrelsresearch.com)

11:07 <_florent_> that's in fact a NiteFury: https://www.crowdsupply.com/rhs-research/nitefury

11:07 <tpb> Title: NiteFury | Crowd Supply (at www.crowdsupply.com)

11:08 <_florent_> has alsmost similar specs than the Numato Aller, and can be found easily between 60/70euros on ebay :)

11:08 <_florent_> i ordered some and will add support for it in litex-boards

11:10 <tnt> Does anyone here have any clue how the vex build system works ? I'm trying to rebuild the vexverilog file while updating the VexRiscV source to the latest master and I've been banging my head against the wall for the paste 90 minutes and made no progress whatsoever.

12:09 <_florent_> tnt: Here are the instructions we are using to build the VexRiscv configurations used in LiteX: https://github.com/litex-hub/pythondata-cpu-vexriscv/blob/master/pythondata_cpu_vexriscv/verilog/README.md

12:09 <tpb> Title: pythondata-cpu-vexriscv/README.md at master · litex-hub/pythondata-cpu-vexriscv · GitHub (at github.com)

12:10 <john_k[m]> florent: I can only find the cle-215+ for much more on eBay

12:12 <tnt> _florent_: yeah, it builds with by default, but I was trying to update the submodule to latest master from the Vex and there that's where it fails.

12:27 <_florent_> john_k[m]: https://www.ebay.fr/itm/SQRL-Acorn-CLE-215-Xilinx-Artix-7-FPGA-M-2/174063380295

12:27 <tpb> Title: SQRL Acorn CLE-215+ Xilinx Artix 7 FPGA M.2 | eBay (at www.ebay.fr)

12:28 <_florent_> or 10: https://www.ebay.fr/itm/Lot-of-10-SQRL-Acorn-FPGA-Crypto-Miner-CLE-215/372843995209

12:28 <tpb> Title: Lot of 10 SQRL Acorn FPGA Crypto Miner CLE-215+ | eBay (at www.ebay.fr)

12:29 <john_k[m]> I saw the French seller, couldn’t find the Uk one tho

12:29 <john_k[m]> Thanks!

12:44 <dkozel> _florent_: the creater of the NiteFury is a GNU Radio user :)

12:45 <dkozel> Wow, that price!

12:49 <_florent_> dkozel: interesting, is he already doing things with it and GNU Radio? if so do you have a link?

12:49 <dkozel> No, his use is unrelated to that board

12:50 <dkozel> There's very little significant, open source and public, use of FPGAs with GNU Radio. Plenty of SDRs that have FPGAs internally, but that's largely opaque to GR

12:51 <dkozel> That will be changing through a few paths over the next year and a bit. My effort is just one of several, hopefully proving out some improvements to generic interface improvements

12:52 <_florent_> just for info, i ordered a lot of 10 Acorn since i'm not sure it these prices will last, once it will be supported in LiteX, if someone is interested, please DM me

12:53 <_florent_> dkozel: i've been doing SDR with LiteX for some years now, but it's mostly only transmitting I/Q samples between a Host and radio chip

12:54 <dkozel> How's your effort on USB PIPE going? I'm very interested in getting these boards working over an external interface such as Thunderbolt and/or USB3

12:54 <_florent_> dkozel: now that it's working fine, we are trying to move some processing to the FPGA

12:54 <dkozel> _florent_: We should chat, there's some really significant stuff going on that's going to be all public and open source

12:55 <dkozel> I saw the SDR on the wiki, is that purchasable?

12:56 <_florent_> dkozel: i'm not selling it directly, but the client is, but i'm not sure about the price for the AD97X version

13:59 <bubble_buster> so to reference a top level pin from _io I do platform.request("foo"), but what if the pin I want is a subsignal? I've tried platform.request("foo.bar"), platform.request("foo").bar and a few other things but I can't get it to work

14:06 <bubble_buster> oh I see. platform.request("foo").bar1 works but platform.request("foo").bar2 doesn't work because you can't request foo twice?

14:29 <zyp> yes

16:24 <john_k[m]> florent: I grabbed one of the CLE-215+ as well

16:54 <pau> Hi guys, I'd like to know your opinion in regards to which board you think would be suitable to learn FPGA using litex that would be cheaper than Nexys4DDR that's used in the tutorial ( https://github.com/litex-hub/fpga_101/tree/master/lab001 ) ?

16:54 <tpb> Title: fpga_101/lab001 at master · litex-hub/fpga_101 · GitHub (at github.com)

17:08 <_florent_> pau: the Arty A7 (35T) is a good board to start with, you should be able to adapt easily most of the lab to it

17:08 <_florent_> we are also planning to suppor the iCEBreaker for this labs

17:12 <pau> thanks _florent_ , the price is less than half, that's much more affordable. I look forward to ICE40LP8K support, hopefully I will be able to contribute if by then I get some skills

17:25 <mithro> pau: If you contribute to projects I care about, I tend to send people hardware

17:45 <pau> thanks mithro , first I want to get good at FPGA, then I can be valuable but first I have to get the skills. I'd be glad to contribute when I'm ready to

17:45 <mithro> @pau FWIW -- Just doing the tutorial and reporting where things don't make sense is already contributing!

17:48 <pau> I will try to get my project opensourced as a tutorial probably. I'm building a robot ( https://www.linkedin.com/posts/activity-6619711870444060672-MqQR ). Want to use the FPGA to control multiple steppers in closed-loop using and incremental encoder. Today I'm using closed loop control on an absolute one that doesn't have good enough resolution.

17:48 <pau> I don't want though to make anybody spend money on a project that might or may not take place.

17:48 <tpb> Title: Pau Carré Cardona posted on LinkedIn (at www.linkedin.com)

18:29 <scanakci> _florent_: thanks for the merge. Once you approve this merge (https://github.com/enjoy-digital/black-parrot/pull/1), I would like to test BP in a fresh VM by directly using the LiteX/python-data repos before you test it. I think it should be good at this point but I would like to ensure that you won't have any issues.

18:29 <tpb> Title: update source files and organize repo by scanakci · Pull Request #1 · enjoy-digital/black-parrot · GitHub (at github.com)

18:32 <scanakci> I also just created an issue related to DRAM tests on Genesys (https://github.com/enjoy-digital/litex/issues/493). I used a previous bitstream that I generated from a ~3 months old LiteDRAM/LiteX to make sure that my FPGA did not die :). It works fine.

18:32 <tpb> Title: DRAM tests fail for Genesys board at 125MhZ · Issue #493 · enjoy-digital/litex · GitHub (at github.com)

18:32 <mithro> scanakci: The auto data push only happens once a day IIRC, I can force it to happen if you poke me

18:33 <scanakci> mithro: I can wait for it. I need to finish some other tasks today.

18:33 <mithro> It's just one or two button clicks

18:34 <scanakci> okay, thanks.