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<futarisIRCcloud>
_florent_: Would it be possible to use the PCIe lane serdes(es) in the Acorn CLE-215 to interface to SGMII for Gigabit Ethernet, NBASE-T, MGBASE-T or 10GBASE-T?
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<daveshah>
I see no reason why not, if you fed it with the right reference clock
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<daveshah>
For 10GBASE-T you would need to use the 4x3.125 interface, I forget what that is called
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<zyp>
XAUI
<daveshah>
yep, thanks
<daveshah>
so many different standards...
<daveshah>
Maybe RXAUI would work too, for two 10GbE links
<zyp>
assuming you can get a phy that supports it
<_florent_>
futarisIRCcloud: i never played with SGMII but i also don't see reasons it would not be possible
<tpb>
Title: communication - What is the exact difference between SGMII and 1000Base-X? - Electrical Engineering Stack Exchange (at electronics.stackexchange.com)
<zyp>
My understanding is that QSGMII is 4x1GbE
<_florent_>
so it's possible there are not that much missing
<zyp>
5GbE would have to be 6.125 because of 8b10b
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<futarisIRCcloud>
ORICO SCM2T3-G40 for 140 USD / 200 AUD does look good.
<tmbinc>
I wonder if PCIe Thunderbolt addon cards ("asus thunderboltex 3" for example is ~70 EUR and commonly available) could be reflashed to act as a thunderbolt device. Chipset is the same (as far as I can judge), but of course all the documentation and configuration tools are only available under NDA
<tmbinc>
It would require a PCIe-to-PCIe base board with power (and CLK maybe?) of course but that should be relatively cheap to make
<tmbinc>
and also the same chips I've found in thunderbolt expansion devices
<tmbinc>
but sure it could be some fusing
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<Claude>
ping dkozel
<dkozel>
Ah hi Claude
<Claude>
(trying to)disassembling the JMS538 firmware at the moment . its a fscking 8051 lol
<dkozel>
I'm working on a schematic for m.2 to USB 3 (physical) in anticipation of the USB PIPE project working. If that happens that could be an option for easy device access
<dkozel>
It gets a bit messy with the power, probably going to skip that to start with
<zyp>
dkozel, m.2 socket to usb or m.2 card with usb?
<dkozel>
Exactly that but with m.2 and USB C sockets
<Claude>
oh that looks pretty cool dkozel
<dkozel>
No credit to me, all the interesting and hard work is _florent_ and bunnie
<dkozel>
I just want to make use of it :D
<bunnie>
lol this one is all florent, he did some amazing work there!
<Claude>
when i scroll up a bit i see a lot of stuff i looked at the last couple of days too :) JHL6540 for example. unfortunatley i was not able to find any information on that part other than marketing pdfs and irclogs at _whitelogger mentioning it
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<john_k[m]>
_florent_: just tested one of the previously non-working CLE-215+ in a new m.2 adapter (instead of the Acorn Nest) and was able to load the bitstream and see the chaser, although rebooting the machine caused it to hang (no monitor attached). I'm still seeing `Error: Unknown flash device (ID 0x00918d0d)` at this point when I try `--flash`. I'm also still seeing some JTAG weirdness when openocd is searching for xc7.tap (reading
<john_k[m]>
mfg 0x7fa, part 0xffff) - at this point I'm suspecting some signal integrity shenanigans so I took off the CLE-215+'s fan at which point JTAG works fine on this unit and it boots fine running litex
<john_k[m]>
should litex enumerate on PCIe as `01:00.0 Memory controller: Xilinx Corporation Device 7024 (rev ff)`?
<john_k[m]>
for the flash, I'm still getting errors, but seeing `Error: Unknown flash device (ID 0x00ffffff)` now
<_florent_>
john_k[m]: rev ff seems weird (should be 01 IIRC), but otherwise it's fine
<CarlFK>
using a pi and netv2 ... openocd.. loaded file top.bit to pld device 0 in 1s 635162us
<CarlFK>
do I have to reset the netv2 to make it take effect?
<bunnie>
no, the bitstream should take effect immediately after it was loaded, if the bitstream was valid for the FPGA
<bunnie>
but if it failed CRC or mismatched to part number it won't take effect
<john_k[m]>
I'm not sure what to think about the SPI Flash - it's obviously working since the FPGA boots the default bitstream. Could it be stuck in QSPI mode or something? Or does the flasher reset the chip out of that?
<bunnie>
yah it has an error saying that the JTAG chain returned all zeros
<bunnie>
so something isn't right. it looks like openOCD decided to go ahead and just blast data across the bus, ignoring the bad TDI signal
<bunnie>
if you're running on a pi4, you might need to tune the BCM2835 clocks line in the alphamax-rpi.cfg file
<bunnie>
i don't know what they need to be tuned to, but it varies from each model of pi. usually i hook up an oscilloscope and just guess values until the timing is right. the values committed to the github master are tuned for the pi3b+
<CarlFK>
bunnie: what openocd source should I use?
<CarlFK>
what I am currently useing is debian stable + the patch you pointed to a few days ago, which needed help patching, and maybe need more than just that patch, so lets go with what you are most confidant in
<CarlFK>
k - let me build that and try again
<bunnie>
yah, this /should/ work -- it's what's shipping in the box.
<bunnie>
you need to, of course, include the bcm2835 target in the config line
<CarlFK>
gcc (GCC) 8.1.0 generates new warnings and thus fails the build. The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and SMUL instructions decoding.
* CarlFK
forks and patches...
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