01:25 <Skip> Thanks @somlo ! Ethernet is up and working under on the pano_logic_g2 with DNS thanks to your help.

01:25 <Skip> root@buildroot:/tmp# ping google.com

01:25 <Skip> loss

11:57 <sajattack[m]> Curious if anyone has tried to bring in WD Swerv core to litex

12:06 <sajattack[m]> Feel free to let me know if that's a dumb question

12:06 <daveshah> I don't think anyone tries, but if it provides one or more Wishbone ports or can be wrapped to provide them it shouldn't be too hard

12:07 <daveshah> If this is for linux-on-litex then it will be no good as it doesn't have an MMU, at least last time I looked

12:07 <sajattack[m]> I think it's axi, not sure

12:07 <daveshah> That's fine, litex has some axi<->wishbone converters

12:09 <sajattack[m]> Not necessarily for linux, I saw it didn't have an mmu. I confirmed it is axi https://github.com/chipsalliance/Cores-SweRV_fpga/blob/master/hardware/design_top/swerv_eh1_reference_design.v

12:09 <tpb> Title: Cores-SweRV_fpga/swerv_eh1_reference_design.v at master · chipsalliance/Cores-SweRV_fpga · GitHub (at github.com)

12:10 <sajattack[m]> Litex is my preferred way of experimenting with riscv cores. I don't know how anyone wires everything up by hand

12:15 <sajattack[m]> all the bajillion inputs and outputs a cpu has I don't understand

14:11 <somlo> sajattack[m]: look in litex/soc/cores/cpu/*/core.py for examples on how to glue cpus to litex

14:11 <somlo> rocket (and probably blackparrot) expose axi interfaces, and get converted to wishbone to hook into the rest of LiteX

14:11 <somlo> the rest of the cpu options (IIRC) all are native wishbone

15:44 <_florent_> sajattack[m]: i started some work on SweRV some time ago, but haven't finished it, in case it could be useful here is what i started: https://gist.github.com/enjoy-digital/641a52b6cbe5f29b989f587ec24e558e

15:44 <tpb> Title: SweRV initial support · GitHub (at gist.github.com)