_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<somlo> Orthogonally to anything, as a relative DT n00b, what's the point of setting address- and size-cells to 2 (https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/json2dts.py#L92) only to then have to prefix a 0x0 before each register address and size value ? :)
<tpb> Title: linux-on-litex-vexriscv/json2dts.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)
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<mithro> zyp: xobs can help with wishbone-tool stuff
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