_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<esden> _florent_: I see you simplified the clock stuff. I was actually hoping to convert that eventually to use the PLL, this is why I was keeping the more complicated setup to be able to add the PLL back in. As far as I can tell we can run the vex at 21MHz or so.
<esden> Also don't we loose the added documentation parts when you remove them from there and remove the AutoDoc stuff?
<esden> I think documentation is a good thing ;)