_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<Claude> _florent_ and daveshah , a question. i'm planing using a DDR1 component on the colorlight i9 SoM (ECP5 45k) , all IO banks are supplied with 3.3V . I have an external circuitry dealing with the SSTL2 levels. Now my question is if you see a problem with that on litedram & nextpnr. Does litedram picks a SSTL2 IO standard on the IO and would nextpnr complain about it? Actually i want LVCMOS33 on the DDR interface
<daveshah> I don't think ecp5 even supports sstl2
<daveshah> The IO standard is set in litex by the platform, not by litedram though
<Claude> Ok so I could probably adjust that to lvcmos . Thanks
<Claude> Ah yes I see , in the traget description
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<_florent_> Claude: DDR1 has not been tested on ECP5, but it's supported on Spartan6 (we only tested SDR and )that's also possible you'll have to do some adaptations or create a specific PHY for DDR1 with ECP5, we only tested SDR and DDR3 with ECP5. DDR1 is working on Spartan6, so LiteDRAM already supports it, but are needed, it will be located to the PHY.
<_florent_> Claude: sorry, i was re-writing my answer...
<Claude> :) _florent_ thanks
<_florent_> Claude: so in short :) : DDR1 has not been tested on ECP5, but is supported on Spartan6, that's possible you'll have to do some adaptation to the PHY
<Claude> Worth a try, have some free time due to a pandemic soon.. good time to get a grip on migen a d LiteX a but deeper
<Claude> ..and LiteX a bit deeper..
<_florent_> Claude: the S6HalfRateDDRPHY supports DDR, LPDDR, DDR2 and DDR3, the ECP5DDRPHY is also a HalfRate PHY and supports DDR3, so by looking at the DDR specific parts in S6HalfRateDDRPHY, you should understand what needs to be modified in the ECP5DDRPHY
<Claude> Cool , thanks for the direction
<Claude> I try to get into it
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<tnt> Claude: did you document the i9 pinout somewhere ?
<Claude> tnt: hmm on paper and twitter a bit. but i'm in the process of tidy all up
<Claude> have also some i9+ incomming, i hope for 85kLE on that :)
<tnt> I'm wondering if they bothered wiring the DQ/DQS lines to the ecp5 dedicated logic for it or if they just ignored it ? For DDR1, at the rates you'll be running it on an ECP5 you can pretty much ignore DQS for reads.
<Claude> yeah thats the point i'm looking right now at. I have the edge connector pinning ready , but need to translate it to actual pin# back. used some hackery "uart on every pin" thing to RE it. but was too lazy to actually send out the real pin#
<tnt> Claude: Hah, I used your hack for the colorlight 75b board rev eng, but I used a rom initialized from the csv to actually send the bga ball number :)
<Claude> ok :) then i used your improved one back on the 75b with the 384 pin ecp5 for some IO hackery :P
<tnt> Ah yeah you made the colorlight to pmod / rpi / hdmi boards rights ? I was thinking I need to order one for the pmod output. Just replaced one side io buf with fet switches for it this morning.
<Claude> Yep :)
<tnt> Are the files somewhere ?
<Claude> I can send the gerbers/Altium , as soon as I'm back at my chair . Currently not at my place
<Claude> Hmm if you want . I have one rpi milled PCB left ..
<tnt> Don't have any rpi :) If you have the spacing / angle that would be enough. I don't have altium, so I wouldn't be able to modify your files, I'll have to redo them if I want some tweaks.
<Claude> Ok give me 30-45 mins . I get you the mechanical parameters
<tnt> Sure, I'm in no hurry tx.
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<_florent_> Claude, tnt: i've also been playing a bit with rev eng bitstreams with Migen/LiteX (i wanted to find some pins that were not yet documented on the Camlink4K and Colorlight), since everything is Python based, you can parse a pinout file (iodb.json from trellis, device package from xilinx for example), create the IOs, add the pin identifier streamers and generate the bitstream very easily :) ex:
<tpb> Title: camlink_4k/ios_streams.py at master · enjoy-digital/camlink_4k · GitHub (at github.com)
<Claude> Oh nice , I try to remember that on the i9+
<Claude> Chances that it is Xilinx based are high too..
<Claude> rotation is 334deg
<Claude> of the connectors
<Claude> step 3d and autocad dwg
<Claude> gerbers,drill and a pdf of the schematic
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<tnt> Claude: tx !
<Claude> It's not a perfect fit , but it fits :)
<tnt> I could always makes the pin holes a bit bigger and solder when it's plugged in :)
<somlo> @florent, @kgugala: litex-on-vexriscv soc driver updated to work on 64bit cpus and 32-bit csr-data-width: https://github.com/gsomlo/linux/tree/litex-devel-2020-03-31-01 -- any comments welcome (github issue here: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/122)
<tpb> Title: GitHub - gsomlo/linux at litex-devel-2020-03-31-01 (at github.com)
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<gregdavill> pdp7: I've just built linux-on-litex with the new orangecrab changes _florent_ pushed.
<gregdavill> I couldn't get the USB interface to come up. So I've been looking into that. After some tweaks I've managed to get the USB interface up and it does seem to work in uploading the rootfs via serialboot
<gregdavill> So the issue you saw where it would hang, is likely just because the usb-core itself is quite fragile with regards to placement seed.
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